View L80223_1117327.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

L80223 10base-t/100base-tx/fx ethernet phy order number r14016 technical manual draft 6/5/00 preliminary
draft 6/5/00 ii rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?ed either the functional descriptions, or the electrical and mechanical speci?cations using production parts. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. db14-000133-00,first edition (june 2000) this document describes revision/release a of lsi logic corporations L80223 10base-t/100base-tx/fx ethernet phy and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design is a registered trademark of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
preface iii rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 preface this book is the primary reference and technical manual for the L80223 10base-t/100base-tx/fx ethernet physical layer device (phy). it contains a complete functional description for the L80223 and includes complete physical and electrical speci?cations for the product. audience this document assumes that you have some familiarity with ethernet devices and related support devices. the people who bene?t from this book are: engineers and managers who are evaluating the device for possible use in a system engineers who are designing the device into a system organization this document has the following chapters: chapter 1, introduction , describes the device in general terms and gives a block diagram and lists the device features. chapter 2, functional description , describes each of the internal blocks in the device in some detail. chapter 3, signal descriptions , lists and describes the device input and output signals. chapter 4, registers , gives a register summary and describes each of the bits in each register. chapter 5, management interface , describes the device management interface, which allows the registers to be read and written.
draft 6/5/00 iv preface rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. chapter 6, speci?cations , lists the ac and dc characteristics and gives typical timing parameters. appendix a, application information , gives practical guidelines for incorporating the device into a design. abbreviations used in this manual below is a list of abbreviations used throughout this manual. 100base-fx 100 mbits/s fiber optic ethernet 100base-t 100 mbits/s twisted-pair ethernet 10base-t 10 mbits/s twisted-pair ethernet 4b5b 4-bit 5-bit clk clock crc cyclic redundancy check crs carrier sense csma carrier sense multiple access cwrd codeword da destination address ecl emitter-coupled logic eof end of frame esd end of stream delimiter fcs frame check sequence fdx full-duplex fef far end fault fifo first in - first out flp fast link pulse hdx half-duplex hiz high impedance i/g individual/group ietf internet engineering task force ipg inter-packet gap iref reference current l/t length and type lsb least-signi?cant bit mib management information base mlt3 multi-level transmission (3 levels) ms millisecond msb most-signi?cant bit mv millivolt nlp normal link pulse nrzi non-return to zero inverted nrz non-return to zero op opcode pcb printed circuit board
draft 6/5/00 preface v rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. conventions used in this manual the ?rst time a word or phrase is de?ned in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111. pf picofarad pre preamble r/lh read latched high r/lhi read latched high with interrupt r/ll read latched low r/lli read latched low with interrupt r/lt read latched transition r/lti read latched transition with interrupt r/wsc read/write self clearing rfc request for comments rj-45 registered jack-45 rmon remote monitoring sa start address or station address sfd start of frame delimiter snmp simple network management protocol soi start of idle ssd start of stream delimiter stp shielded twisted pair tp twisted pair m h microhenry m p microprocessor utp unshielded twisted pair
draft 6/5/00 vi preface rev. a copyright ? 2000 by lsi logic corporation. all rights reserved.
L80223 10base-t/100base-tx/fx ethernet phy vii rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 contents chapter 1 introduction 1.1 overview 1-1 1.2 features 1-4 chapter 2 functional description 2.1 overview 2-2 2.1.1 channel operation 2-2 2.1.2 data paths 2-2 2.2 block diagram description 2-7 2.2.1 oscillator and clock 2-8 2.2.2 controller interface 2-9 2.2.3 encoder 2-14 2.2.4 decoder 2-16 2.2.5 scrambler 2-17 2.2.6 descrambler 2-17 2.2.7 twisted-pair transmitters 2-19 2.2.8 twisted-pair receivers 2-24 2.2.9 fx transmitter and receiver 2-27 2.2.10 clock and data recovery 2-30 2.2.11 link integrity and autonegotiation 2-31 2.2.12 link indication 2-35 2.2.13 collision 2-35 2.2.14 led drivers 2-37 2.3 start of packet 2-40 2.3.1 100 mbits/s 2-40 2.3.2 10 mbits/s 2-41 2.4 end of packet 2-41 2.4.1 100 mbits/s 2-41 2.4.2 10 mbits/s 2-42
draft 6/5/00 viii contents rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. 2.5 full/half duplex mode 2-43 2.5.1 forcing full/half duplex operation 2-43 2.5.2 full/half duplex indication 2-44 2.5.3 loopback 2-44 2.6 repeater mode 2-45 2.7 10/100 mbits/s selection 2-46 2.7.1 forcing 10/100 mbits/s operation 2-46 2.7.2 autoselecting 10/100 mbits/s operation 2-46 2.7.3 10/100 mbits/s indication 2-46 2.8 jabber 2-47 2.9 automatic jam 2-47 2.9.1 100 mbits/s jam 2-47 2.9.2 10 mbits/s jam 2-47 2.10 reset 2-48 2.11 powerdown 2-48 2.12 receive polarity correction 2-49 chapter 3 signal descriptions 3.1 media interface signals 3-2 3.2 controller interface signals (mii) 3-4 3.3 management interface 3-5 3.4 miscellaneous signals 3-6 3.5 leds 3-7 3.6 power supply 3-10 chapter 4 registers 4.1 bit types 4-2 4.2 mi serial port register summary 4-4 4.3 registers 4-7 4.3.1 control register (register 0) 4-7 4.3.2 status register (register 1) 4-9 4.3.3 phy id 1 register (register 2) 4-11 4.3.4 phy id 2 register (register 3) 4-12 4.3.5 autonegotiation advertisement register (register 4) 4-13 4.3.6 autonegotiation remote end capability register (register 5) 4-15
draft 6/5/00 contents ix rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.7 con?guration 1 register (register 16) 4-17 4.3.8 con?guration 2 register (register 17) 4-20 4.3.9 status output register (register 18) 4-23 4.3.10 interrupt mask register (register 19) 4-25 4.3.11 reserved register (register 20) 4-28 chapter 5 management interface 5.1 signal description 5-2 5.2 general operation 5-3 5.3 multiple register access 5-5 5.4 frame structure 5-6 5.5 register structure 5-8 5.6 interrupts 5-9 chapter 6 speci?cations 6.1 absolute maximum ratings 6-2 6.2 electrical characteristics 6-3 6.2.1 twisted-pair dc characteristics 6-5 6.2.2 fx characteristics, transmit 6-9 6.3 ac electrical characteristics 6-12 6.3.1 25 mhz input/output clock timing characteristics 6-13 6.3.2 transmit timing characteristics 6-14 6.3.3 receive timing characteristics 6-17 6.3.4 collision and jam timing characteristics 6-23 6.3.5 link pulse timing characteristics 6-27 6.3.6 jabber timing characteristics 6-30 6.4 led driver timing characteristics 6-31 6.4.1 mi serial port timing characteristics 6-32 6.5 pinouts and package drawings 6-34 6.5.1 pinouts 6-34 6.5.2 L80223 pin layout 6-40 6.6 mechanical drawing 6-41 appendix a application information a.1 example schematics a-1 a.2 tp transmit interface a-5 a.3 tp receive interface a-6
draft 6/5/00 x contents rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. a.4 tp transmit output current set a-7 a.5 cable selection a-8 a.6 transmitter droop a-9 a.7 automatic jam a-9 a.8 fx interface a-11 a.8.1 connection to 3.3 v transceivers a-11 a.8.2 connection to 5 v transceivers a-12 a.8.3 disabling the fx interface a-14 a.9 mii controller interface a-15 a.9.1 clocks a-15 a.9.2 output drive a-15 a.9.3 mii disable a-16 a.9.4 receive output enable a-17 a.10 fbi controller interface a-17 a.11 serial port a-18 a.11.1 polling and interrupt a-18 a.11.2 multiple register access a-19 a.11.3 serial port addressing a-19 a.12 oscillator a-21 a.13 led drivers a-21 a.14 repeater applications a-22 a.14.1 mii-based repeaters a-22 a.14.2 non-mii based repeaters a-22 a.14.3 clocks a-23 a.15 power supply decoupling a-24 customer feedback
draft 6/5/00 xi rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. figures 1.1 top level block diagram 1-3 2.1 L80223 device block diagram 2-3 2.2 100base-tx/fx and 10base-t frame format 2-4 2.3 mii frame format 2-5 2.4 tp output voltage template 2-20 2.5 tp input voltage template (10 mbits/s) 2-25 2.6 link pulse output voltage template (10 mbits/s) 2-32 2.7 nlp vs flp link pulse 2-33 2.8 soi output voltage template - 10 mbits/s 2-42 3.1 device logic diagram 3-2 5.1 mi serial port frame timing diagram 5-4 5.2 mi serial frame structure 5-6 5.3 mdio interrupt pulse 5-10 6.1 25 mhz output timing 6-13 6.2 transmit timing - 100 mbits/s 6-15 6.3 transmit timing - 10 mbits/s 6-16 6.4 receive timing, start of packet - 100 mbits/s 6-19 6.5 receive timing, end of packet - 100 mbits/s 6-20 6.6 receive timing, start of packet - 10 mbits/s 6-21 6.7 receive timing, end of packet - 10 mbits/s 6-22 6.8 rx_en timing 6-22 6.9 collision timing, receive 100 mbits/s 6-24 6.10 collision timing, receive 10 mbits/s 6-24 6.11 collision timing, transmit - 100 mbits/s 6-25 6.12 collision timing, transmit - 10 mbits/s 6-25 6.13 collision test timing 6-25 6.14 jam timing 6-26 6.15 nlp link pulse timing 6-29 6.16 flp link pulse timing 6-29 6.17 jabber timing 6-30 6.18 led driver timing 6-31 6.19 mi serial port timing 6-33 6.20 mdio interrupt pulse timing 6-33 6.21 L80223 64-pin lqfp, top view 6-40 6.22 64-pin lqfp mechanical drawing 6-42 a.1 typical network interface adapter card schematic
draft 6/5/00 xii rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. using the L80223 a-2 a.2 typical switching port schematic using L80223 a-3 a.3 typical external phy schematic using L80223 a-4 a.4 connection to 3.3 v fiber optic transceivers a-12 a.5 connection to 5 v fiber optic transceivers a-13 a.6 mii output driver characteristics a-16 a.7 serial device port address selection a-20
draft 6/5/00 xiii rev. a copyright ? 2000 by lsi logic corporation. all rights reserved. tables 2.1 transmit preamble and sfd bits at mac nibble interface 2-5 2.2 receive preamble and sfd bits at mac nibble interface 2-6 2.3 4b/5b symbol mapping 2-10 2.4 4b/5b symbol mapping 2-14 2.5 tp output voltage - 10 mbits/s 2-21 2.6 transmit level adjust 2-22 2.7 fx transmit level adjust 2-27 2.8 pled_[1:0] output select bit encoding 2-38 2.9 led normal function de?nition 2-38 2.10 led event de?nition 2-39 4.1 mi register bit type de?nition 4-2 5.1 mi serial port register summary 5-8 6.1 absolute maximum ratings 6-2 6.2 dc characteristics 6-3 6.3 twisted pair characteristics (transmit ) 6-5 6.4 twisted pair characteristics (receive ) 6-8 6.5 fx characteristics, transmit 6-9 6.6 fx characteristics, receive 6-11 6.7 test conditions 6-12 6.8 25 mhz input/output clock 6-13 6.9 transmit timing 6-14 6.10 receive timing 6-17 6.11 collision and jam timing 6-23 6.12 link pulse timing 6-27 6.13 jabber timing 6-30 6.14 led driver timing 6-31 6.15 mi serial port timing 6-32 6.16 L80223 pin list (by signal category) 6-34 6.17 L80223 pin list (by pin number) 6-37 a.1 tp transformer speci?cation a-5 a.2 tp transformer sources a-5 a.3 cable con?guration a-8 a.4 crystal speci?cations a-21
draft 6/5/00 xiv rev. a copyright ? 2000 by lsi logic corporation. all rights reserved.
L80223 10base-t/100base-tx/fx ethernet phy 1-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 chapter 1 introduction this chapter contains a brief introduction to the L80223 10base-t/100base-tx/fx ethernet physical layer device (phy). it contains the following sections: section 1.1, overview section 1.2, features 1.1 overview this manual describes the L80223 device. the device contains a single phy channel. the convention used in this manual is that device refers to the ic, and channel refers to the phy in the device. the L80223 is a highly-integrated analog interface ic for twisted-pair or ?ber optic ethernet applications. the device can be con?gured for either 100 mbits/s (100base-tx or 100base-fx) or 10 mbits/s (10base-t) ethernet operation. the phy channel contains the following blocks: 4b5b encoder/manchester encoder scrambler 10base-t transmitter 100base-tx transmitter 100base-fx transmitter 10base-t receiver 100base-tx receiver 100base-fx receiver
draft 6/5/00 1-2 introduction copyright ? 2000 by lsi logic corporation. all rights reserved. clock and data recovery autonegotiation and link integrity descrambler 4b5b decoder/manchester decoder mii controller interface management interface (mi) collision detection figure 1.1 is a simpli?ed top-level block diagram of the L80223 device.
draft 6/5/00 overview 1-3 rev. letter copyright ? 2000 by lsi logic corporation. all rights reserved. figure 1.1 top level block diagram oscin interface serial controller collision 4b5b encoder scrambler 4b5b decoder descrambler clock recovery & data auto- and link negotiation recovery clock & data (manchester decoder) manchester encoder oscillator led drivers port (mi) squelch squelch (mii) controller ethernet leds 100base-tx transmitter 10base-t transmitter 100base-tx receiver 10base-t receiver L80223 100base-fx transmitter 100base-fx receiver tpi/fxo tpo/fxi
draft 6/5/00 1-4 introduction copyright ? 2000 by lsi logic corporation. all rights reserved. internal output waveshaping circuitry and on-chip ?lters in the phy eliminates the need for external ?lters normally required in 100base-tx and 10base-t applications. using the on-chip autonegotiation algorithm, the device can automatically con?gure the phy channel to independently operate in 100 mbits/s or 10 mbits/s operation in either full- or half-duplex mode. the device uses the management interface (mi) serial port to access 11 16-bit registers in the phy. these registers comply to clause 22 of ieee 802.3u and contain bits and ?elds that re?ect con?guration inputs, status outputs, and device capabilities. the device is ideally suited as a media interface for 10base-t/100base-tx/fx repeaters, routers, pcmcia cards, nic cards, motherboards, networked modems, and other end station applications. the device is implemented in 0.35 or 0.30 micron cmos technology and operates on a 3.3 v power supply. the outputs are 5v-tolerant and directly interface to other 5v devices. 1.2 features the following list summarizes the salient features of the device: single-chip solution for a 10base-t/100base-tx/fx phy dual speed: 10/100 mbit/s half-duplex or full-duplex operation mii interface to ethernet mac management interface (mi) for con?guration and status optional repeater interface autonegotiation for 10/100 mbit/s, full/half duplex operation advertisement control through pins all applicable ieee 802.3, 10base-t and 100base-tx/fx speci?cations are met on-chip wave shaping (no external ?lters required)
draft 6/5/00 features 1-5 copyright ? 2000 by lsi logic corporation. all rights reserved. adaptive equalizer for 100base-tx operation baseline wander correction minimum number of external components independent programmable led output pins re?ect the following events: C link C activity C collision C full-duplex C speed (10/100 mbits/s) 3.3 v power supply, 5 v tolerant i/o 64-pin lqfp
draft 6/5/00 1-6 introduction copyright ? 2000 by lsi logic corporation. all rights reserved.
L80223 10base-t/100base-tx/fx ethernet phy 2-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 chapter 2 functional description this chapter contains a functional description of the phy device. it has the following sections: section 2.1, overview section 2.2, block diagram description section 2.3, start of packet section 2.4, end of packet section 2.5, full/half duplex mode section 2.6, repeater mode section 2.7, 10/100 mbits/s selection section 2.8, jabber section 2.9, automatic jam section 2.10, reset section 2.11, powerdown section 2.12, receive polarity correction
draft 6/5/00 2-2 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.1 overview this section gives a brief overview of the device functional operation. the L80223 is a complete 10/100 mbits/s ethernet media interface ic. a block diagram is shown in figure 2.1 . 2.1.1 channel operation the phy operates in the 100base-tx or 100base-fx modes at 100 mbits/s, or in the 10base-t mode at 10 mbits/s. the 100 mbits/s modes and the 10 mbits/s mode differ in data rate, signaling protocol, and allowed wiring as follows: 100base-tx mode uses two pairs of category 5 or better utp or stp twisted-pair cable with 4b5b encoded, scrambled, and mlt3 coded 62.5-mhz ternary data to achieve a throughput of 100 mbits/s. the 100base-fx mode uses two ?ber cables with 4b5b encoded, 125-mhz binary data to achieve a throughput of 100 mbits/s. 10 mbits/s mode uses two pairs of category 3 or better utp or stp twisted-pair cable with manchester encoded 10-mhz binary data to achieve a 10 mbits/s throughput the data symbol format on the twisted-pair cable for the 100 and 10 mbits/s modes is de?ned in ieee 802.3 speci?cations and shown in figure 2.2 . 2.1.2 data paths in each device, there is a transmit data path and a receive data path associated with each phy channel. the transmit data path is from the controller interface to the twisted-pair transmitter. the receive data path is from the twisted-pair receiver to the controller interface.
draft 6/5/00 overview 2-3 rev. letter copyright ? 2000 by lsi logic corporation. all rights reserved. figure 2.1 L80223 device block diagram clock generator pll oscin resetn rx_en/jamn rptr interface tx_clk txd[3:0] mdc mdio serial controller tx_en tx_er/txd4 rx_clk rxd[3:0] crs rx_dv rx_er/rxd4 collision 4b5b encoder scrambler mlt3 encoder switched clock generator lp filter 100base-tx transmitter rom dac lp filter + - 4b5b decoder descrambler clock recovery & data auto- & link negotiation adaptive equalizer lp filter tpo +/ fxi - tpo -/ fxi + + - 100base-tx receiver 10base-tx receiver recovery clock & data (manchester decoder) manchester encoder 10base-t receiver oscillator col pled[3:0]n mda[3:0]n led drivers port (mi) vdd[6:1] gnd[6:1] current sources pll squelch +/- vth + - + +/- vth + - + squelch mlt3 encoder (mii pled[5:4]n rext + - 100base-fx transmitter +/- vth + - + 100base-tx receiver + - vth sd_thr sd/fxdisn tpi +/ fxo - tpi -/ fxo + mdintn/mda4n or fbi)
draft 6/5/00 2-4 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. figure 2.2 100base-tx/fx and 10base-t frame format interframe gap preamble sfd da sa ln llc data fcs interframe gap ethernet mac frame ssd da sa ln llc data fcs 100base-tx data symbols idle preamble sfd esd idle idle = ssd = preamble = sfd = da, sa, ln, llc data, fcs = esd = [ 1 1 1 1 ...] [ 1 1 0 0 0 1 0 0 0 1 ] [ 1 0 1 0 ...] 62 bits long [ 1 1 ] [ data ] [ 0 1 1 0 1 0 0 1 1 1 ] before/after 4b5b encoding, scrambling, and mlt3 coding da sa ln llc data fcs 10base-t data symbols idle preamble sfd soi idle idle = preamble = sfd = da, sa, ln, llc data, fcs = [ no transitions ] [ 1 1 ] [ data ] [ 1 1 ] with no mid bit soi = transition [ 1 0 1 0 ...] 62 bits long before/after manchester encoding ssd da sa ln llc data fcs 100base-fx data symbols idle preamble sfd esd idle idle = ssd = preamble = sfd = da, sa, ln, llc data, fcs = esd = [ 1 1 1 1 ...] [ 1 1 0 0 0 1 0 0 0 1 ] [ 1 0 1 0 ...] 62 bits long [ 1 1 ] [ data ] [ 0 1 1 0 1 0 0 1 1 1 ] before/after 4b5b encoding
draft 6/5/00 overview 2-5 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.1.2.1 100base-tx in 100base-tx transmit operation, data is received on the controller interface from an external ethernet controller according to the format shown in figure 2.3 and table 2.1 . the data is sent to the 4b5b encoder, which scrambles the encoded data. the scrambled data is then sent to the tp transmitter. the tp transmitter converts the encoded and scrambled data into mlt3 ternary format, preshapes the output, and drives the twisted-pair cable. figure 2.3 mii frame format table 2.1 transmit preamble and sfd bits at mac nibble interface signals bit value txdo x x 1 1 1. 1st preamble nibble transmitted. 11111111111111 2 2. 1st sfd nibble transmitted. 1d0 3 3. 1st data nibble transmitted. d4 4 4. d0 through d7 are the ?rst 8 bits of the data ?eld. txd1 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d1 d5 txd2 x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d2 d6 txd3 x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d3 d7 tx_en 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 prmble sfd data 1 tx_en = 1 preamble = sfd = datan = idle = [ 1 0 1 0 ...] 62 bits long [ 1 1 ] [between 64 - 1518 data bytes] [tx_en = 0] tx_en = 0 idle preamble start of frame data nibbles data 2 data n-1 data n 62 bits 2 bits a. mii frame format b. mii nibble order d0 d1 d2 d3 d4 first bit mac serial bit stream d5 d6 d7 lsb txd2/rxd2 txd3/rxd3 tx_en = 0 idle msb second nibble txd0/rxd0 txd1/rxd1 first nibble mii nibble stream
draft 6/5/00 2-6 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. in 100base-tx receive operation, the tp receiver takes incoming encoded and scrambled mlt3 data from the twisted-pair cable, removes any high-frequency noise from the input, equalizes the input signal to compensate for the effects of the cable, performs baseline wander correction, quali?es the data with a squelch algorithm, and converts the data from mlt3-encoded levels to internal digital levels. the output of the receiver then goes to a clock and data recovery block that recovers a clock from the incoming data, uses the clock to latch valid data into the device, and converts the data back to nrz format. the 4b5b decoder and descrambler then decodes and unscrambles the nrz data, respectively, and sends it out of the controller interface to an external ethernet controller. the format of the received data at the controller interface is as shown in table 2.2 . 2.1.2.2 100base-fx 100base-fx operation is similar to 100base-tx operation except: the transmit output/receive input is not scrambled or mlt3 encoded the transmit data is output to a fx transmitter instead of the tp waveshaper/ transmitter the receive data is input to the fx ecl level detector instead of the equalizer and associated tp circuitry the fx interface has a signal detect input table 2.2 receive preamble and sfd bits at mac nibble interface signals bit value rxdo x 1 1 111111111111111 2 1d0 3 d4 4 rxd1 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d1 d5 rxd2 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d2 d6 rxd3 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d3 d7 rx_dv 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1. first preamble nibble received. depending on the mode, the device may eliminate either all or some of the preamble nibbles, up to the ?rst sfd nibble. 2. first sfd nibble received. 3. first data nibble received. 4. d0 through d7 are the ?rst 8 bits of the data ?eld.
draft 6/5/00 block diagram description 2-7 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.1.2.3 10base-t 10base-t operation is similar to the 100base-tx operation except: there is no scrambler/descrambler the encoder/decoder is manchester instead of 4b5b the data rate is 10 mbits/s instead of 100 mbits/s, the twisted-pair symbol data is two-level manchester instead of ternary mlt-3. the transmitter generates link pulses during the idle period the transmitter detects the jabber condition the receiver detects link pulses and implements the autonegotiation algorithm 2.2 block diagram description the L80223 phy device has the following main blocks: oscillator and clock controller interface 4b5b/manchester encoder/decoder scrambler/descrambler twisted-pair transmitters fiber transmitter twisted-pair receivers fiber receiver clock and data recovery autonegotiation/link integrity descrambler collision detection led drivers a management interface (mi) serial port provides access to 11 internal phy registers.
draft 6/5/00 2-8 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. figure 2.1 shows the main blocks, along with their associated signals. the following sections describe each of the blocks in figure 2.1 . the performance of the device in both the 10 and 100 mbits/s modes is described. 2.2.1 oscillator and clock the L80223 requires a 25 mhz reference frequency for internal signal generation. this 25 mhz reference frequency is generated with either an external 25 mhz crystal connected between oscin and gnd or with the application of an external 25-mhz clock to oscin. the device provides either a 2.5-mhz or 25-mhz reference clock at the tx_clk or rx_clk output pins for 10-mhz or 100-mhz operation, respectively.
draft 6/5/00 block diagram description 2-9 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.2 controller interface this section describes the controller interface operation. the L80223 has two interfaces to an external controller: media independent interface (mii) five bit interface (fbi) 2.2.2.1 mii interface the device has an mii interface to an external ethernet media access controller (mac). mii (100 mbits/s) C the mii is a nibble wide packet data interface de?ned in ieee 802.3 and shown in figure 2.3 . the L80223 meets all the mii requirements outlined in ieee 802.3. the L80223 can directly connect, without any external logic, to any ethernet controller or other device that also complies with the ieee 802.3 mii speci?cations. the mii interface contains the following signals: transmit data bits (txd[3:0]) transmit clock (tx_clk) transmit enable (tx_en) transmit error (tx_er) receive data bits (rxd[3:0]) receive clock (rx_clk) carrier sense (crs) receive data valid (rx_dv) receive data error (rx_er) collision (col) the transmit and receive clocks operate at 25 mhz in 100 mbits/s mode. on the transmit side, the tx_clk output runs continuously at 25 mhz. when no data is to be transmitted, tx_en must be deasserted. while tx_en is deasserted, tx_er and txd[3:0] are ignored and no data is clocked into the device. when tx_en is asserted on the rising edge of tx_clk, data on txd[3:0] is clocked into the device on the rising edge
draft 6/5/00 2-10 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. of the tx_clk output clock. txd[3:0] input data is nibble wide packet data whose format must be the same as speci?ed in ieee 802.3 and shown in figure 2.3 . when all data on txd[3:0] has been latched into the device, tx_en must be deasserted on the rising edge of tx_clk. tx_er is also clocked in on the rising edge of tx_clk. tx_er is a transmit error signal. when this signal is asserted, the device substitutes an error nibble in place of the normal data nibble that was clocked in on txd[3:0]. the error nibble is de?ned to be the /h/ symbol, which is de?ned in ieee 802.3 and shown in table 2.3 . table 2.3 4b/5b symbol mapping symbol name description 5b code 4b code 0 data 0 0b11110 0b0000 1 data 1 0b01001 0b0001 2 data 2 0b10100 0b0010 3 data 3 0b10101 0b0011 4 data 4 0b01010 0b0100 5 data 5 0b01011 0b0101 6 data 6 0b01110 0b0110 7 data 7 0b01111 0b0111 8 data 8 0b10010 0b1000 9 data 9 0b10011 0b1001 a data a 0b10110 0b1010 b data b 0b10111 0b1011 c data c 0b11010 0b1100 d data d 0b11011 0b1101 e data e 0b11100 0b1110 f data f 0b11101 0b1111 i idle 0b11111 0b0000
draft 6/5/00 block diagram description 2-11 copyright ? 2000 by lsi logic corporation. all rights reserved. because the oscin input clock generates the tx_clk output clock, the txd[3:0], tx_en, and tx_er signals are also clocked in on rising edges of oscin. on the receive side, as long as a valid data packet is not detected, crs and rx_dv are deasserted and the rxd[3:0] signals are held low. when the start of packet is detected, crs and rx_dv are asserted on the falling edge of rx_clk. the assertion of rx_dv indicates that valid data is clocked out on rxd[3:0] on the falling edge of the rx_clk. the rxd[3:0] data has the same frame structure as the txd[3:0] data and is speci?ed in ieee 802.3 and shown in figure 2.3 . when the end of the packet is detected, crs and rx_dv are deasserted, and rxd[3:0] is held low. crs and rx_dv also stay deasserted if the device is in the link fail state. rx_er is a receive error output that is asserted when certain errors are detected on a data nibble. rx_er is asserted on the falling edge of rx_clk for the duration of that rx_clk clock cycle during which the nibble containing the error is output on rxd[3:0]. the collision output, col, is asserted whenever the collision condition is detected. mii (10 mbits/s) C mii 10 mbits/s operation is identical to 100 mbits/s operation except: j ssd #1 0b11000 0b0101 k ssd #2 0b10001 0b0101 t esd #1 0b01101 0b0000 r esd #2 0b00111 0b0000 h halt 0b00100 unde?ned C invalid codes all others 1 0b0000* 1. these 5b codes are not used. the decoder decodes these 5b codes to 4b 0000. the encoder encodes 4b 0000 to 5b 11110, as shown in symbol data 0. table 2.3 4b/5b symbol mapping (cont.) symbol name description 5b code 4b code
draft 6/5/00 2-12 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. the tx_clk and rx_clk clock frequency is reduced to 2.5 mhz tx_er is ignored rx_er is disabled and always held low receive operation is modi?ed as follows: on the receive side, when the squelch circuit determines that invalid data is present on the tp inputs, the receiver is idle. during idle, rx_clk follows tx_clk, rxd[3:0] is held low, and crs and rx_dv are deasserted. when a start of packet is detected on the tp receive inputs, crs is asserted and the clock recovery process starts on the incoming tp input data. after the receive clock has been recovered from the data, the rx_clk is switched over to the recovered clock and the data valid signal rx_dv is asserted on a falling edge of rx_clk. once rx_dv is asserted, valid data is clocked out on rxd[3:0] on the falling edge of rx_clk. the rxd[3:0] data has the same packet structure as the txd[3:0] data and is formatted on rxd[3:0] as speci?ed in ieee 802.3 and shown in figure 2.3 . when the end of packet is detected, crs and rx_dv are deasserted. crs and rx_dv also stay deasserted as long as the device is in the link fail state. 2.2.2.2 fbi interface the five bit interface (also referred to as fbi) is a ?ve-bit wide interface that is produced when the 4b5b encoder/decoder is bypassed. the fbi is primarily used for repeaters or ethernet controllers that have integrated encoder/decoders. the fbi is identical to the mii except: the fbi data path is ?ve bits wide, not nibble wide like the mii the tx_er pin is recon?gured to be the ?fth transmit data bit (txd4) the rx_er pin is recon?gured to be the ?fth receive data bit (rxd4) crs is asserted as long as the device is in the link pass state col is not valid rx_dv is not valid the tx_en pin is ignored
draft 6/5/00 block diagram description 2-13 copyright ? 2000 by lsi logic corporation. all rights reserved. there is no fbi operation in the 10 mbits/s mode. 2.2.2.3 selection of mii or fbi fbi selection C the fbi is automatically enabled when the 4b5b encoder/decoder is bypassed. bypassing the encoder/decoder passes the 5b symbols between the receiver/transmitter directly to the fbi without any alterations or substitutions. to bypass the 4b5b encoder/decoder, set the bypass encoder bit (byp_enc) in the mi serial port con?guration 1 register. when the fbi is enabled, it may also be desirable to bypass the scrambler/descrambler and disable the internal crs loopback function. to bypass the scrambler/descrambler, set the bypass scrambler bit (byp_scr) in the mi serial port con?guration 1 register. to disable the internal crs loopback, set the tx_en to crs loopback disable bit (txen_crs) in the mi serial port con?guration 1 register. mii selection C to disable the mii (and fbi) inputs and outputs, set the mii_dis bit in the mi serial port control register. when the mii is disabled, the mii and fbi inputs are ignored, and the mii, fbi, and tpi outputs are placed in a high-impedance state. the mii pins affected are: rx_clk rxd[3:0] rx_dv rx_er col if the mi address lines, mda[4:0]n, are pulled high during reset or powerup, the L80223 powers up and resets with the mii and fbi disabled. otherwise, the L80223 powers up and resets with the mii and fbi enabled. in addition, when the r/j_cfg bit in the mi serial port con?guration 1 register is low, the rx_en/jamn pin is con?gured for rx_en operation. if the rx_en pin is low in this situation, the mii controller interface outputs are placed in the high-impedance state.
draft 6/5/00 2-14 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.3 encoder this section describes the 4b5b encoder, which is used in 100 mbits/s operation. it also describes the manchester encoder, used in 10base-t operation. 2.2.3.1 4b5b encoder (100 mbits/s) 100base-tx operation requires that the data be 4b5b encoded. the 4b5b encoder block shown in figure 2.1 converts the four-bit data nibbles into ?ve-bit data words. the mapping of the 4b nibbles to 5b codewords is speci?ed in ieee 802.3 and is shown in table 2.4 . table 2.4 4b/5b symbol mapping symbol name description 5b code 4b code 0 data 0 11110 0000 1 data 1 01001 0001 2 data 2 10100 0010 3 data 3 10101 0011 4 data 4 01010 0100 5 data 5 01011 0101 6 data 6 01110 0110 7 data 7 01111 0111 8 data 8 10010 1000 9 data 9 10011 1001 a data a 10110 1010 b data b 10111 1011 c data c 11010 1100 d data d 11011 1101 e data e 11100 1110 f data f 11101 1111 i idle 11111 0000
draft 6/5/00 block diagram description 2-15 copyright ? 2000 by lsi logic corporation. all rights reserved. the 4b5b encoder takes 4b (four-bit) nibbles from the transmit mac block, converts them into 5b (?ve-bit) words according to table 2.4 , and sends the 5b words to the scrambler. the 4b5b encoder also substitutes the ?rst eight bits of the preamble with the start of stream delimiter (ssd) (/j/k/ symbols) and adds an end of stream delimiter (esd) (/t/r/ symbols) to the end of each packet, as de?ned in ieee 802.3 and shown in figure 2.2 . the 4b5b encoder also ?lls the period between packets (idle period), with a continuous stream of idle symbols, as shown in figure 2.2 . 2.2.3.2 manchester encoder (10 mbits/s) the manchester encoder shown in figure 2.1 is used for 10 mbits/s operation. it combines clock and non-return to zero inverted (nrzi) data such that the ?rst half of the data bit contains the complement of the data, and the second half of the data bit contains the true data, as speci?ed in ieee 802.3. this process guarantees that a transition always occurs in the middle of the bit cell. the manchester encoder on the device converts the 10 mbits/s nrzi data from the ethernet controller interface into a single data stream for the tp transmitter and adds a start of idle pulse (soi) at the end of the packet as speci?ed in ieee 802.3 and shown in figure 2.2 . the manchester encoding process is only done on actual packet data; during the idle period between packets, no signal is transmitted except for periodic link pulses. j ssd #1 11000 0101 k ssd #2 10001 0101 t esd #1 01101 0000 r esd #2 00111 0000 h halt 00100 unde?ned --- invalid codes all others 1 0000 1. these 5b codes are not used. the decoder converts them to a 4b code of 0000. the encoder converts the 4b 0000 code to the 5b 11110 code, as shown in symbol 0. table 2.4 4b/5b symbol mapping (cont.) symbol name description 5b code 4b code
draft 6/5/00 2-16 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.3.3 encoder bypass setting the bypass encoder/decoder bit (byp_enc) in the mi serial port con?guration 1 register bypasses the 4b5b encoder. when this bit is set, 5b code words are passed directly from the controller interface to the scrambler without any of the alterations described in section 2.2.3.1, 4b5b encoder (100 mbits/s), page 2-14 . setting the bit automatically places the device in the fbi mode as described in the subsection entitled fbi selection on page 2-13 . 2.2.4 decoder this section describes the 4b5b decoder, used in 100 mbits/s operation, which converts 5b encoded data to 4b nibbles. it also describes the manchester decoder, used in 10base-t operation. 2.2.4.1 4b5b decoder (100 mbits/s) because the tp input data is 4b5b encoded on the transmit side, the 4b5b decoder must decode it on the receive side. the mapping of the 5b codewords to the 4b nibbles is speci?ed in ieee 802.3. the 4b5b decoder takes the 5b codewords from the descrambler, converts them into 4b nibbles according to table 2.4 , and sends the 4b nibbles to the receive ethernet controller. the 4b5b decoder also strips off the ssd delimiter (/j/k/ symbols), and replaces it with two 4b data 5 nibbles (/5/ symbol). it also strips off the esd delimiter (/t/r/ symbols), and replaces it with two 4b data 0 nibbles (/i/ symbol), per ieee 802.3 speci?cations (see figure 2.2 ). the 4b5b decoder detects ssd, esd, and codeword errors in the incoming data stream as speci?ed in ieee 802.3. to indicate these errors, the device asserts the rx_er output as well as the ssd, esd, and cwrd bits in the mi serial port status output register while the errors are being transmitted across rxd[3:0]. 2.2.4.2 manchester decoder (10 mbits/s) in manchester coded data, the ?rst half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. the manchester decoder converts the single data stream from the tp receiver into non-return to zero (nrz) data for the controller
draft 6/5/00 block diagram description 2-17 copyright ? 2000 by lsi logic corporation. all rights reserved. interface. to do this, it decodes the data and strips off the soi pulse. because the clock and data recovery block has already separated the clock and data from the tp receiver, that block inherently performs the the manchester decoding. 2.2.4.3 decoder bypass setting the bypass encoder/decoder bit (byp_enc) in the mi serial port con?guration 1 register bypasses the 4b5b decoder. when this bit is set, 5b code words are passed directly to the controller interface from the descrambler without any of the alterations described in section 2.2.4, decoder, page 2-16 . additionally, the crs pin is continuously asserted whenever the device is in the link pass state. setting the bit automatically places the device in the fbi mode as described in the subsection entitled fbi selection on page 2-13 . 2.2.5 scrambler 100base-tx transmission requires scrambling to reduce the radiated emissions on the twisted pair. the scrambler takes the nrzi encoded data from the 4b5b encoder, scrambles it per the ieee 802.3 speci?cations, and sends it to the tp transmitter. a scrambler is not used for 10 mbits/s operation. 2.2.5.1 scrambler bypass setting the bypass encoder/decoder bit (byp_scr) in the mi serial port con?guration 1 register bypasses the scrambler. when this bit is set, 5b data bypasses the scrambler and goes directly to the 100base-tx transmitter. 2.2.6 descrambler the descrambler block shown in figure 2.1 is used in 100base-tx operation. the device descrambler takes the scrambled nrzi data from the data recovery block, descrambles it according to ieee 802.3 speci?cations, aligns the data on the correct 5b word boundaries, and sends it to the 4b5b decoder. the algorithm for synchronization of the descrambler is the same as the algorithm outlined in the ieee 802.3 speci?cation.
draft 6/5/00 2-18 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. after the descrambler is synchronized, it maintains synchronization as long as enough descrambled idle pattern ones are detected within a given interval. to stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern ones in a 1 ms interval. if 25 consecutive descrambled idle pattern ones are not detected within the 1 ms interval, the descrambler goes out of synchronization and restarts the synchronization process. if the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit (loss_sync) is set in the mi serial port status output register. the bit stays set until the descrambler achieves synchronization. the descrambler is disabled for 10base-t operation. 2.2.6.1 descrambler bypass setting the bypass encoder/decoder bit (byp_scr) in the mi serial port con?guration 1 register bypasses the descrambler. when this bit is set, 5b data bypasses the descrambler and goes directly from the 100base-t receiver to the 4b5b decoder.
draft 6/5/00 block diagram description 2-19 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.7 twisted-pair transmitters this section describes the operation of the 10 and 100 mbits/s tp transmitters. 2.2.7.1 100 mbits/s tp transmitter the tp transmitter consists of an mlt3 encoder, waveform generator, and line driver. the mlt3 encoder converts the nrzi data from the scrambler into a three-level code required by ieee 802.3. mlt3 coding uses three levels, converting ones to transitions between the three levels, and zeros to no transitions or changes in level. the purpose of the waveform generator is to shape the transmit output pulse. the waveform generator takes the mlt3 three level encoded waveform and uses an array of switched current sources to control the shape of the twisted-pair output signal. the waveform generator consists of switched current sources, a clock generator, ?lter, and logic. the switched current sources control the rise and fall time as well as signal level to meet ieee 802.3 requirements. the output of the switched current sources goes through a second order low-pass ?lter that smooths the current output and removes any high-frequency components. in this way, the waveform generator preshapes the output waveform transmitted onto the twisted-pair cable such that the waveform meets the pulse template requirements outlined in ieee 802.3. the waveform generator eliminates the need for any external ?lters on the tp transmit output. the line driver converts the shaped and smoothed waveform to a current output that can drive greater than 100 meters of category 5 unshielded twisted-pair cable or 150-ohm shielded twisted-pair cable. 2.2.7.2 10 mbits/s tp transmitter even though the 10 mbits/s transmitter operation is much different than that of 100 mbits/s, it also consists of a waveform generator and line driver (see figure 2.1 ). the waveform generator, which consists of a rom, dac, clock generator, and ?lter, shapes the output transmit pulse. the dac
draft 6/5/00 2-20 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. generates a stair-stepped representation of the desired output waveform. the stairstepped dac output then is passed through a low-pass ?lter to smooth the dac output and remove any high-frequency components. the dac values are determined from the data at the rom addresses. the data is chosen to shape the pulse to the desired template. the clock generator clocks the data into the dac at high speed. in this way, the waveform generator preshapes the output waveform to be transmitted onto the twisted-pair cable to meet the pulse template requirements outlined in ieee 802.3 clause 14 and shown in figure 2.4 and table 2.5 . the waveshaper replaces and eliminates external ?lters on the tp transmit output. the line driver converts the shaped and smoothed waveform to a current output that can drive greater than 100 meters of category 3/4/5 100-ohm unshielded twisted-pair cable or 150-ohm shielded twisted-pair cable without any external ?lters. during the idle period, no output signals are transmitted on the tp outputs except for link pulses. figure 2.4 tp output voltage template 1.0 0.8 0.6 0.4 0.2 0.0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 01020 30405060708090100110 time (ns) voltage (v) a b c d e g n o p q t v w u r l k j m f h i s
draft 6/5/00 block diagram description 2-21 copyright ? 2000 by lsi logic corporation. all rights reserved. t table 2.5 tp output voltage - 10 mbits/s reference time (ns) internal mau voltage (v) a0 0 b 15 1.0 c 15 0.4 d 25 0.55 e 32 0.45 f39 0 g57 - 1.0 h 48 0.7 i 67 0.6 j89 0 k74 - 0.55 l73 - 0.55 m61 0 n 85 1.0 o 100 0.4 p 110 0.75 q 111 0.15 r 111 0 s 111 - 0.15 t 110 - 1.0 u 100 - 0.3 v 110 - 0.7 w90 - 0.7
draft 6/5/00 2-22 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.7.3 transmit level adjust the transmit output current level is derived from an internal reference voltage and the external resistor on the rext pin. the transmit level can be adjusted with either: the external resistor on the rext pin, or the four transmit level adjust bits (tlvl[3:0]) in the mi serial port con?guration 1 register as shown in table 2.6 . the adjustment range is approximately -14% to +16% in 2% steps. table 2.6 transmit level adjust tlvl[3:0] bits gain 0000 1.16 0001 1.14 0010 1.12 0011 1.10 0100 1.08 0101 1.06 0110 1.04 0111 1.02 1000 1.00 1001 0.98 1010 0.96 1011 0.94 1100 0.92 1101 0.90 1110 0.88 1111 0.86
draft 6/5/00 block diagram description 2-23 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.7.4 transmit rise and fall time adjust the transmit output rise and fall time can be adjusted with the two transmit rise/fall time adjust bits (trf[1:0]) in the mi serial port con?guration 1 register. the adjustment range is - 0.25 ns to +0.5 ns in 0.25 ns steps. 2.2.7.5 stp (150 ohm) cable mode the transmitter can be con?gured to drive 150 w shielded twisted-pair cable. to enable this con?guration, set the cable type select bit (cable) in the mi serial port con?guration 1 register. when stp mode is enabled, the output current is automatically adjusted to comply with ieee 802.3 levels. 2.2.7.6 transmit activity indication appropriately setting the programmable led output select bits in the mi serial port led con?guration 2 register programs transmit activity to appear on some of the pled[5:0]n pins. when one or more of the pled[5:0]n pins is programmed to be an activity or transmit activity detect output, that pin is asserted low for 100 ms every time a transmit packet occurs. the pled[5:0]n outputs are open-drain with resistor pullup and can drive an led from v dd or can drive other digital inputs. see section 2.2.14, led drivers, page 2-37 for more detailed information on the led outputs. 2.2.7.7 transmit disable setting the transmit disable bit (xmt_dis) in the mi serial port con?guration 1 register disables the tp transmitter. when the bit is set, the tp transmitter is forced into the idle state, no data is transmitted, no link pulses are transmitted, and internal loopback is disabled. 2.2.7.8 transmit powerdown setting the transmit powerdown bit (xmt_pdn) in the mi serial port con?guration 1 register powers down the tp transmitter. when the bit is set, the tp transmitter is powered down, the tp transmit outputs are high impedance, and the rest of the L80223 operates normally.
draft 6/5/00 2-24 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.8 twisted-pair receivers the device is capable of operating at either 10- or 100-mbits/s. this section describes the twisted-pair receivers and squelch operation for both modes of operation. 2.2.8.1 100 mbits/s tp receiver the tp receiver detects input signals from the twisted-pair input and converts them to a digital data bit stream ready for clock and data recovery. the receiver can reliably detect 100base-tx compliant transmitter data that has been passed through 0 to 100 meters of 100 w category 5 utp or 150-ohm stp cable. the 100 mbits/s receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and an mlt3 decoder. the tp inputs ?rst go to an adaptive equalizer. the adaptive equalizer compensates for the low-pass characteristics of the cable, and can adapt and compensate for 0 to 100 meters of category 5, 100-ohm or 150-ohm stp cable. the baseline wander correction circuit restores the dc component of the input waveform that the external transformers have removed. the comparators convert the equalized signal back to digital levels and qualify the data with the squelch circuit. the mlt3 decoder takes the three-level mlt3 encoded output data from the comparators and converts it to normal digital data to be used for clock and data recovery. 2.2.8.2 10 mbits/s tp receiver the 10 mbits/s receiver detects input signals from the twisted-pair cable that are within the template shown in figure 2.5 the tp inputs are biased by internal resistors and go through a low-pass ?lter designed to eliminate any high-frequency input noise. the output of the receive ?lter goes to two different types of comparators: squelch and zero crossing. the squelch comparator determines whether the signal is valid, and the zero crossing comparator senses the actual data transitions after the signal is determined to be valid. the output of the squelch comparator goes to the squelch circuit and is also used for link pulse detection, soi detection, and reverse polarity detection. the output of the zero-crossing comparator is used for clock and data recovery in the manchester decoder.
draft 6/5/00 block diagram description 2-25 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 2.5 tp input voltage template (10 mbits/s) 2.2.8.3 squelch (100 mbits/s) the squelch block determines if the tp input contains valid data. the 100 mbits/s tp squelch is one of the criteria used to determine link integrity. the squelch comparators compare the tp inputs against ?xed positive and negative thresholds, called squelch levels. the output from the squelch comparator goes to a digital squelch circuit, which determines whether the receive input data on that port is valid. if the data is invalid, the receiver is in the squelched state. if the input voltage exceeds the squelch levels at least four times with alternating polarity within a 10 m s interval, the squelch circuit determines that the data is valid and the receiver enters into the unsquelch state. in the unsquelch state, the receive threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. when the receiver is in the unsquelch state, the input signal is considered valid. the device stays in the unsquelch state until loss of data is detected. loss of data is detected if no alternating polarity unsquelch transitions short bit 585 mv sin ( p * t/pw) 0pw 585 mv 3.1 v slope 0.5 v/ns 585 mv 3.1 v long bit 585 mv sin[2 p (t - pw2)/pw)] 585 mv sin ( p * t/pw) slope 0.5 v/ns 0 pw/4 3pw/4 pw
draft 6/5/00 2-26 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. are detected during any 10 m s interval. when a loss of data is detected, the receive squelch is turned on again. 2.2.8.4 squelch (10 mbits/s) the tp squelch algorithm for 10 mbits/s mode is identical to the 100 mbits/s mode, except: the 10 mbits/s tp squelch algorithm is not used for link integrity, but to sense the beginning of a packet the receiver goes into the unsquelch state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50 to 250 ns interval the receiver goes into the squelch state when soi is detected unsquelch detection has no effect on link integrity (link pulses are used in 10 mbits/s mode for that purpose) start of packet is determined when the receiver goes into the unsquelch state and crs is asserted the receiver meets the squelch requirements de?ned in ieee 802.3 clause 14. 2.2.8.5 equalizer disable setting the equalizer disable bit (eqlzr) in the mi serial port con?guration 1 register disables the adaptive equalizer. when disabled, the equalizer is forced into the response it would normally have if zero cable length was detected. 2.2.8.6 receive level adjust setting the receive level adjust bit (rlv0) in the mi serial port con?guration 1 register lowers the receiver squelch and unsquelch levels by 4.5 db. setting this bit may allow the device to support longer cable lengths. 2.2.8.7 receive activity indication appropriately setting the programmable led output select bits in the mi serial port led con?guration 2 register programs receive activity to appear on some of the pled[5:0]n pins. when one or more of the
draft 6/5/00 block diagram description 2-27 copyright ? 2000 by lsi logic corporation. all rights reserved. pled[5:0]n pins is programmed to be a receive activity or activity detect output, that pin is asserted low for 100 ms every time a receive packet occurs. the pled[5:0]n outputs are open-drain with resistor pullup and can drive an led from v dd or can drive another digital input. see section 2.2.14, led drivers, page 2-37 for more detailed information on the led outputs. 2.2.9 fx transmitter and receiver the fx transmitter and receiver implement the 100base-fx function de?ned in ieee 802.3. 100base-fx is intended for transmission and reception of data over ?ber and is speci?ed to operate at 100 mbits/s. thus, the fx transmitter and receiver in the device only operate when the device is placed in 100 mbits/s mode. 2.2.9.1 transmitter the fx transmitter converts data from the 4b5b encoder into binary nrzi data and outputs the data onto the fxo+/- pins. the output driver is a differential current source that is able to drive a 100 w load to ecl levels. the fxo+/- pins can directly drive an external ?ber optic transceiver. the fx transmitter meets all the requirements de?ned in ieee 802.3. the fx transmit output current level is derived from an internal reference voltage and the external resistor on the rext pin. the fx transmit level can be adjusted with this resistor or it can also be adjusted with the two fx transmit level adjust bits (fxlvl[1:0]) in the mi serial port mask register as shown in table 2.7 . table 2.7 fx transmit level adjust fxlvl[1:0] bits gain 11 1.30 10 1.15 01 0.85 00 1.00
draft 6/5/00 2-28 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.9.2 receiver the fx receiver: converts the differential ecl inputs on the fxi+/- pins to a digital bit stream validates the data on fxi+/- with the sd/fxdisn input pin enable or disables the fx interface with the sd/fxdisn pin. the fx receiver meets all requirements de?ned in ieee 802.3. the input to the fxi+/- pins can be directly driven from a ?ber optic transceiver and ?rst goes to a comparator. the comparator compares the input waveform against the internal ecl threshold levels to produce a low jitter serial bit stream with internal logic levels. the data from the comparator output is then passed to the clock and data recovery block, provided that the signal detect input, sd/fxdisn, is asserted. signal detect C the fx receiver has a signal detect input pin, sd/fxdisn, which indicates whether the incoming data on fxi+/- is valid or not. the sd/fxdisn input can be driven directly from an external ?ber optic transceiver and meets all requirements de?ned in the ieee 802.3 speci?cations. the sd/fxdisn input goes directly to a comparator. the comparator compares the input waveform against the internal ecl threshold level to produce a digital signal with internal logic levels. the output of the signal detect comparator then goes to the link integrity and squelch blocks. if the sd/fxdisn input is asserted, the device is placed in the link pass state and the input data on fxi+/- is determined to be valid. if the sd/fxdisn input is deasserted, the device is placed in the link fail state and the input data on fxi+/- is determined to be invalid. the sd_thr pin adjusts the ecl trip point of the sd/fxdisn input. when the sd_thr pin is tied to a voltage between gnd and gnd + 0.45v, the trip point of the sd/fxdisn ecl input buffer is internally set to vdd - 1.3 v. when the sd_thr pin is set to a voltage greater than gnd + 0.85 v, the trip point of the sd/fxdisn ecl input buffer is set to the voltage that is applied to the sd_thr pin. the trip level for the sd/fxdisn input buffer must be set to vdd - 1.3 v. having external control of the sd/fxdisn buffer trip level with the sd_thr pin allows this trip level to be referenced to an external supply, which facilitates
draft 6/5/00 block diagram description 2-29 copyright ? 2000 by lsi logic corporation. all rights reserved. connection to an external ?ber optic transceiver. if the device is to be connected to a 3.3v external ?ber optic transceiver, sd_thr must be tied to gnd. if the device is to be connected to a 5v external ?ber optic transceiver, sd_thr must be tied to vdd - 1.3v, which can be accomplished with an external resistor divider. refer to the appendix a, application information for more details on connections to external ?ber optic transceivers. 2.2.9.3 fx disable the fx interface is disabled if the sd/fxdisn pin is connected to gnd; otherwise, the fx interface is enabled. disabling the fx interface automatically enables the tp interface. conversely, enabling the tp interface disables the fx interface.
draft 6/5/00 2-30 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.10 clock and data recovery this section describes clock and data recovery methods implemented in the device for both the 100 mbits/s and 10 mbits/s modes. 2.2.10.1 100 mbits/s clock and data recovery clock recovery is accomplished with a phase-locked-loop (pll). if valid data is not present on the receive inputs, the pll is locked to the 25-mhz tx_clk signal. when the squelch circuit detects valid data on the receive tp input, and if the device is in the link pass state, the pll input is switched to the incoming data on the receive inputs. the pll then locks on to the transitions in the incoming signal to recover the clock. the recovered data clock is then used to generate the 25 mhz nibble clock, rx_clk, which clocks data into the controller interface section. the recovered clock extracted by the pll latches in data from the tp receiver to perform data recovery. the data is then converted from a single bit stream into nibble wide data words according to the format shown in figure 2.3 2.2.10.2 10 mbits/s clock and data recovery the clock recovery process for 10 mbits/s mode is identical to the 100 mbits/s mode except: the recovered clock frequency is a 2.5 mhz nibble clock the pll is switched from tx_clk to the tp input when the squelch indicates valid data the pll takes up to 12 transitions (bit times) to lock onto the preamble, so some of the preamble data symbols are lost. however, the clock recovery block recovers enough preamble symbols to pass at least six nibbles of preamble to the receive controller interface as shown in figure 2.3 . the data recovery process for 10 mbits/s mode is identical to that of the 100 mbits/s mode. as mentioned in the manchester decoder section, the data recovery process inherently performs decoding of manchester encoded data from the tp inputs.
draft 6/5/00 block diagram description 2-31 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.11 link integrity and autonegotiation the device can be con?gured to implement either the standard link integrity algorithms or the autonegotiation algorithm. the standard link integrity algorithms are used solely to establish a link to and from a remote device. the autonegotiation algorithm is used to establish a link to and from a remote device and automatically con?gure the device for 10 or 100 mbits/s and half or full duplex operation. the different standard link integrity algorithms for 10 and 100 mbits/s modes are described in following subsections. the autonegotiation algorithm in the device meets all requirements speci?ed in ieee 802.3. autonegotiation is only speci?ed for 100base-tx and 10base-t operation, and must be disabled when the device is placed in 100base-fx mode. 2.2.11.1 10base-t link integrity algorithm (10 mbits/s) the device implements the same 10base-t link integrity algorithm de?ned in ieee 802.3. this algorithm uses normal link pulses (nlps), which are transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called link pass state). the transmit link pulse meets the template requirements de?ned in ieee 802.3 and shown in figure 2.6 . refer to ieee 802.3 for more details if needed.
draft 6/5/00 2-32 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. figure 2.6 link pulse output voltage template (10 mbits/s) 2.2.11.2 100base-tx link integrity algorithm (100 mbits/s) because the ieee 802.3 speci?cation de?nes 100base-tx to have an active idle signal, there is no need to have separate link pulses such as those de?ned for 10base-t. the L80223 uses the squelch criteria and descrambler synchronization algorithm on the input data to determine if the device has successfully established a link with a remote device (called link pass state). refer to ieee 802.3 for more details if needed. 2.2.11.3 autonegotiation algorithm as stated previously, the autonegotiation algorithm is used for two purposes: to establish a link to and from a remote device to automatically con?gure the device for either 10 or 100 mbits/s operation and either half- or full-duplex operation. the autonegotiation algorithm is the same algorithm de?ned in ieee 802.3 clause 28. autonegotiation uses a burst of link pulses, called fast link pulses (flps), to pass up to 16 bits of signaling data back and forth between the L80223 and a remote device. the transmit flp pulses meet 0 bt 1.3 bt 2.0 bt + 50 mv - 50 mv 42.0 bt 2.0 bt 0.85 bt - 3.1 v 585 mv 3.1 v 0.5 v/ns + 50 mv - 50 mv 0.5 bt 0.6 bt 300 mv 4.0 bt 4.0 bt 200 mv 0.25 bt
draft 6/5/00 block diagram description 2-33 copyright ? 2000 by lsi logic corporation. all rights reserved. the template speci?ed in ieee 802.3 and shown in figure 2.6 . a timing diagram contrasting nlps and flps is shown in figure 2.7 . figure 2.7 nlp vs flp link pulse any of the following events initiates the autonegotiation algorithm: power up device reset the autonegotiation enable (aneg_en) bit in the mi serial port control register for that port is cleared, then set the autonegotiation reset (aneg_rst) bit in the mi serial port control register is set the channel enters the link fail state once a negotiation has been initiated, the device ?rst determines if the remote device has autonegotiation capability. if the remote device is not autonegotiation capable and is just transmitting either 10base-t or 100base-tx signals, the device senses it and places itself in the same mode as the remote device. if the device detects flps from the remote device, the remote device is determined to have autonegotiation capability, and the device then uses the contents of the mi serial port autonegotiation advertisement register for that port to advertise its capabilities to the remote device. the remote device does the same, and the capabilities read back from the remote device are stored in the mi serial port autonegotiation normal link pulse (nlp) tpo tpo fast link pulse (flp) clock clock clock clock clock clock clock data data data data data data d0 d1 d2 d3 d14 d15
draft 6/5/00 2-34 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. remote end capability register. the L80223 negotiation algorithm then matches its capabilities to the remote device's capabilities and determines the device con?guration according to the priority resolution algorithm de?ned in ieee 802.3 clause 28. when the negotiation process is completed, the L80223 then con?gures itself for either 10 or 100 mbits/s mode and either full- or half-duplex modes (depending on the outcome of the negotiation process), and it switches to either the 100base-tx or 10base-t link integrity algorithms (depending on which mode was enabled through autonegotiation). refer to ieee 802.3 clause 28 for more details. 2.2.11.4 autonegotiation outcome indication the outcome or result of the autonegotiation process is stored in the 10/100 speed detect (spd_det) and duplex detect (dplx_det) bits in the mi serial port status output register. 2.2.11.5 autonegotiation status to monitor the status of the autonegotiation process, simply read the autonegotiation acknowledgement (aneg_ack) bit in the mi serial port status register. the aneg_ack bit is 1 when an autonegotiation has been initiated and successfully completed. 2.2.11.6 autonegotiation enable to enable the autonegotiation algorithm, set the autonegotiation enable bit (aneg_en) in the mi serial port control register, or assert the aneg pin. to disable the autonegotiation algorithm, clear the aneg_en bit, or deassert the aneg pin. when the autonegotiation algorithm is enabled, the device halts all transmissions including link pulses for 1200 to 1500 ms, enters the link fail state, and restarts the negotiation process. when the autonegotiation algorithm is disabled, the selection of 100 mbits/s or 10 mbits/s mode is determined with the speed bit in the mi serial port control register, and the selection of half- or full-duplex mode determined from the state of the dplx bit in the mi serial port control register.
draft 6/5/00 block diagram description 2-35 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.11.7 autonegotiation reset appropriately setting the autonegotiation reset (aneg_rst) bit in the mi serial port control register can initiate or reset the autonegotiation algorithm at any time. 2.2.12 link indication receive link detect activity can be monitored through the link detect bit (link) in the mi serial port status register and the link fail detect bit (lnk_fail) in the status output register. link detect activity can also be programmed to appear on the pled3n or pled0n pins. to do this, appropriately set the programmable led output select bits in the mi serial port con?guration 2 register as shown in table 2.9 . when either the pled3n or pled0n pins are programmed to be a link detect output, they are asserted low whenever the device is in the link pass state. the pled3 output is an open-drain pin with pullup resistor and can drive an led from v dd . the pled0 output has both pullup and pulldown driver transistors in addition to a weak pullup resistor, so it can drive an led from either v dd or gnd. both the pled3n and pled0n outputs can also drive another digital input. refer to section 2.2.14, led drivers, page 2-37 for a description on how to program the pled[3:0]n pins and their default values. 2.2.13 collision collisions occur whenever transmit and receive operations occur simultaneously while the device is in half-duplex mode. 2.2.13.1 100 mbits/s in 100 mbits/s operation, a collision occurs and is sensed whenever there is simultaneous transmission (packet transmission on tpo+/-) and reception (non-idle symbols detected at the tpi+/- input). when a collision is detected, the col output is asserted, tp data continues to be transmitted on the twisted-pair outputs, tp data continues to be received on the twisted-pair inputs, and internal crs loopback is disabled. after a collision is in process, crs is asserted and stays asserted until the receive and transmit packets that caused the collision are terminated.
draft 6/5/00 2-36 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. the collision function is disabled if the device is in the full-duplex mode, is in the link fail state, or if the device is in the diagnostic loopback mode. 2.2.13.2 10 mbits/s a collision in the 10 mbits/s mode is identical to one the 100 mbits/s mode except: the 10 mbits/s squelch criteria determines reception the rxd[3:0] outputs are all forced low the collision signal (col) is asserted when the sqe test is performed the collision signal (col) is asserted when the jabber condition has been detected. 2.2.13.3 collision test to test the controller interface collision signal (col), set the coltst bit in the mi serial port control register. when this bit is set, tx_en is looped back onto col and the tp outputs are disabled. 2.2.13.4 collision indication collisions are indicated through the col pin, which is asserted high every time a collision occurs. the device can also be programmed to indicate collisions on the pled2n output. in the mi serial port con?guration 2 register, set the led function select bits (led_def_[1:0]) so that collision activity is indicated at the pled2n output. set the pled2_[1:0] bits in the same register to 0b11 (normal). with these settings, a led connected to the pled2n pin will re?ect collision activity. when the pled2n pin is programmed to be a collision detect output, it is asserted low for 100 ms every time a collision occurs. the pled2n output is open drain with a pullup resistor and can drive an led from v dd or can drive another digital input. see section 2.2.14, led drivers, page 2-37 for more details on how to program the led output pins to indicate various conditions.
draft 6/5/00 block diagram description 2-37 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.2.14 led drivers the pled[5:2]n outputs are open-drain with a pullup resistor and can drive leds tied to v dd . the pled[1:0]n outputs have both pullup and pulldown driver transistors with a pullup resistor, so the pled[1:0]n outputs can drive leds tied to either v dd or gnd. the pled[5:0]n outputs can be programmed through the mi serial port con?guration 2 register for the following functions: normal function on off blink the pled[5:0]n outputs are programmed with the led output select bits (pled_[1:0]) and the led normal function select bits (led_def[1:0]) in the mi serial port con?guration register. 2.2.14.1 led output select bits there are four sets of output select bits in mi serial port con?guration register, one set for each led output pin: pled3_[1:0] control the pled3n output pled2_[1:0] control the pled2n output pled1_[1:0] control the pled1n output pled0_[1:0] control the pled0n output the pledx_[1:0] bits program the outputs to operate in the following modes: normal operation (see section 2.2.14.2, led normal function select bits ) blink steady on (pled[3:0]n pin low) steady off (pled[3:0]n pin high)
draft 6/5/00 2-38 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. table 2.8 shows the encoding of the output select bits. 2.2.14.2 led normal function select bits when the pled[5:0]n pins are programmed for their normal functions (pled_[1:0] = 0b11), the pin output states indicate four speci?c types of events. the led normal function select bits (led_def[1:0]) in the mi serial port con?guration register determine the states of the pins, as indicated in table 2.9 and table 2.10 . table 2.8 pled_[1:0] output select bit encoding pled_[1] pled_[0] led state led pin 1 1 normal led pin re?ects the functions selected with the led_def[1:0] bits 1 0 led blink led output driver continuously toggles at a rate of 100 ms on, 100 ms off 0 1 led on led output driver is low 0 0 led off led output driver is high table 2.9 led normal function de?nition led_def[1:0] pled5n pled4n pled3n pled2n pled1n pled0n 0b11 rcv act xmt act link col fdx 10/100 0b10 rcv act xmt act link act fdx 10/100 0b01 rcv act xmt act link + act col fdx 10/100 0b00 1 rcv act xmt act link 100 act fdx link10 1. the L80223 powers up with the led_def[1:0] bits set to the default value of 0b00.
draft 6/5/00 block diagram description 2-39 copyright ? 2000 by lsi logic corporation. all rights reserved. the default normal functions for pled[5:0]n are receive activity, transmit activity, link 100, activity, full duplex, and link 10, respectively. table 2.10 led event de?nition symbol de?nition rcv act receive activity occurred, stretch pulse to 100 ms xmt act transmit activity occurred, stretch pulse to 100 ms link 100 or 10 mbits/s link detected link+act 100 or 10 mbits/s link detected or activity occurred, stretch pulse to 100 ms (link detect causes led to be on, activity causes led to blink) act activity occurred, stretch pulse to 100 ms link100 100 mbit/s link detected col collision occurred, stretch pulse to 100 ms fdx full-duplex mode enabled 10/100 10 mbits/s mode enabled (high), or 100 mbits/s mode enabled (low) link10 10 mbits/s link detected
draft 6/5/00 2-40 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.3 start of packet this section describes start of packet operation for both the 100 mbits/s and 10 mbits/s modes. 2.3.1 100 mbits/s a unique start of stream delimiter (ssd) indicates the start of packet for 100 mbits/s mode. the ssd pattern consists of two /j/k/ 5b symbols inserted at the beginning of the packet in place of the ?rst two preamble symbols, as de?ned in ieee 802.3 clause 24 and shown in table 2.4 and figure 2.2 . the 4b5b encoder generates the transmit ssd and inserts the /j/k/ symbols at the beginning of the transmit data packet in place of the ?rst two 5b symbols of the preamble, as shown in figure 2.2 . the 4b5b decoder detects the receive pattern. to do this, the decoder examines groups of 10 consecutive code bits (two 5b words) from the descrambler. between packets, the receiver detects the idle pattern (5b /i/ symbols). when in the idle state, the device deasserts the crs and rx_dv pins. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /j/k/ symbols, the start of packet is detected, data reception begins, and /5/5/ symbols are substituted in place of the /j/k/ symbols. if the receiver is in the idle state and 10 consecutive code bits from the receiver are a pattern that is neither /i/i/ nor /j/k/ symbols, but contain at least two noncontiguous zeros, activity is detected but the start of packet is considered to be faulty and a false carrier indication (also referred to as bad ssd) is signaled to the controller interface. when false carrier is detected, crs is asserted, rx_er is asserted, rx_dv remains deasserted, the rxd[3:0] output state is 0b1110 while rx_er is asserted, and the start of stream error bit (ssd) is set in the mi serial port status output register. once a false carrier event is detected, the idle pattern (two /i/i/ symbols) must be detected before any new ssds can be sensed.
draft 6/5/00 end of packet 2-41 copyright ? 2000 by lsi logic corporation. all rights reserved. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /i/i/ nor /j/k/ symbols but does not contain at least two noncontiguous zeros, the data is ignored and the receiver stays in the idle state. 2.3.2 10 mbits/s because the idle period in 10 mbits/s mode is de?ned to be when there is no valid data on the tp inputs, the start of packet for 10 mbits/s mode is detected when the tp squelch circuit detects valid data. when the start of packet is detected, crs is asserted as described in section 2.2.2, controller interface, page 2-9 . see section 2.2.8.4, squelch (10 mbits/s), page 2-26 for details on the squelch algorithm. 2.4 end of packet this section describes end of packet operation for both the 100 mbits/s and 10 mbits/s modes. 2.4.1 100 mbits/s the end of stream delimiter (esd) indicates the end of packet for 100 mbits/s mode. the esd pattern consists of two /t/r/ 4b5b symbols inserted after the end of the packet, as de?ned in ieee 802.3 clause 24 and shown in table 2.4 and figure 2.2 . the 4b5b encoder generates the transmit esd and inserts the /t/r/ symbols after the end of the transmit data packet, as shown in figure 2.2 . the 4b5b decoder detects the esd pattern when there are groups of 10 consecutive code bits (two 5b words) from the descrambler during valid packet reception. if the 10 consecutive code bits from the receiver during valid packet reception consist of the /t/r/ symbols, the end of packet is detected, data reception is terminated, the crs and rx_dv pins are asserted, and /i/i/ symbols are substituted in place of the /t/r/ symbols. if 10 consecutive code bits from the receiver during valid packet reception do not consist of /t/r/ symbols, but instead consist of /i/i/
draft 6/5/00 2-42 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. symbols, the packet is considered to have been terminated prematurely and abnormally, and the end of packet condition is signalled to the controller interface. when the premature end of packet condition is detected, the rx_er signal is asserted for the nibble associated with the ?rst /i/ symbol detected, then the crs and rx_dv pins are deasserted. the device also sets end of stream error bit (esd) in the mi serial port status output register to indicate the premature end of packet condition. 2.4.2 10 mbits/s the end of packet for 10 mbits/s mode is indicated with the soi (start of idle) pulse. the soi pulse is a positive double wide pulse containing a manchester code violation inserted at the end of every packet. the tp transmitter generates the transmit soi pulse and inserts it at the end of the data packet after tx_en has been deasserted. the transmit waveshaper shapes the transmitted soi output pulse at the tp output to meet the pulse template requirements speci?ed in ieee 802.3 clause 14 and shown in figure 2.8 . figure 2.8 soi output voltage template - 10 mbits/s 0 bt 4.5 bt 6.0 bt + 50 mv - 50 mv 45.0 bt 4.5 bt 2.5 bt - 3.1 v 0.25 bt 2.25 bt 585 mv 3.1 v 0.5 v/ns 585 mv sin (2 *p* (t/1 bt)) 0 t 0.25 bt and 225 t 2.5 bt
draft 6/5/00 full/half duplex mode 2-43 copyright ? 2000 by lsi logic corporation. all rights reserved. the tp receiver senses missing data transitions in order to detect the receive soi pulse. once the soi pulse is detected, data reception is ended and the crs and rx_dv pins are deasserted. 2.5 full/half duplex mode half-duplex mode is the csma/cd operation de?ned in ieee 802.3. it allows transmission or reception, but not both at the same time. full- duplex operation is a mode that allows simultaneous transmission and reception. full duplex in the 10 mbits/s mode is identical to operation in the 100 mbits/s mode. the device can be forced into either the full- or half-duplex mode, or the device can use autonegotiation to autoselect full/half-duplex operation. when the device is placed in full-duplex mode: the collision function is disabled, and tx_en to crs loopback is disabled 2.5.1 forcing full/half duplex operation to independently force a channel into either the full- or half-duplex mode, set the duplex mode select (dplx) bit in the mi serial port control register, or assert the dplx pin, assuming that autonegotiation is not enabled with the aneg_en bit in the mi serial port control register. the device automatically con?gures itself for full- or half-duplex mode. to do this, the device uses the autonegotiation algorithm to advertise and detect full and half duplex capabilities to and from a remote device. to enable autonegotiation, set the autonegotiation enable (aneg_en) bit in the mi serial port control register or assert the aneg pin. to select the advertised full/half duplex capability, appropriately set the bits in the mi serial port autonegotiation advertisement register. autonegotiation functionality is described in more detail in section 2.2.11, link integrity and autonegotiation .
draft 6/5/00 2-44 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.5.2 full/half duplex indication full duplex detection can be monitored through the duplex detect bit (dplx_det) in the mi serial port status output register. the device can also be programmed such that the full-duplex indication appears on the pled1n pin. to do this, appropriately set the programmable led output select bits in the mi serial port con?guration 2 register as described in table 2.9 . when the pled1n pin is programmed to be a full-duplex detect output, it is asserted low when the device is con?gured for full duplex operation. the pled1 output has both pullup and pulldown driver transistors and a weak pullup resistor, so it can drive an led from either v dd or gnd and can also drive a digital input. 2.5.3 loopback 2.5.3.1 internal crs loopback tx_en is internally looped back onto crs during every transmit packet. this internal crs loopback is disabled during collision, in full-duplex mode, in the link fail state, and when the transmit disable bit (xmt_dis) is set in the mi serial port con?guration 1 register. in 10 mbits/s mode, internal crs loopback is also disabled when jabber is detected. 2.5.3.2 diagnostic loopback setting the loopback bit (lpbk) in the mi serial port control register selects the diagnostic loopback mode. when diagnostic loopback is enabled, the txd[3:0] data is looped back onto rxd[3:0], tx_en is looped back onto crs, rx_dv operates normally, the tp receive and transmit paths are disabled, the transmit link pulses are halted, and the half/full duplex modes do not change. diagnostic loopback cannot be enabled when in the fbi mode (see section 2.2.2.2, fbi interface, page 2-12 ).
draft 6/5/00 repeater mode 2-45 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.6 repeater mode the L80223 uses the standard mii as the physical interface for mii-based repeater cores. the L80223 has one prede?ned repeater mode. to enable this mode, assert the rptr pin. when this repeater mode is enabled with the rptr pin: tx_en to crs loopback is disabled autonegotiation is disabled 100 mbits/s operation is enabled half-duplex operation is enabled note: enabling the repeater mode with the rptr pin is only one of many possible repeater modes available on the device. other repeater modes are available when appropriate reg- ister bits are set to enable or disable the desired functions for a given repeater mode type. for additional information, see section a.14, repeater applications, page a-22 .
draft 6/5/00 2-46 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.7 10/100 mbits/s selection the device can be forced into either the 10 or 100 mbits/s mode, or it can use autonegotiation to autoselect 10 or 100 mbits/s operation. 2.7.1 forcing 10/100 mbits/s operation to independently force each channel into either the 10 mbits/s or 100 mbits/s mode: clear the aneg_en bit in the mi serial port control register, and appropriately set the speed select (speed) bit in the mi serial port control register. alternatively, if the aneg pin is low, the speed pin controls the speed. asserting the speed pin high forces 100 mbits/s operation and deasserting it low forces 10 mbits/s operation. 2.7.2 autoselecting 10/100 mbits/s operation the device can automatically con?gure itself for 10 or 100 mbits/s mode. to do this, it uses the autonegotiation algorithm to advertise and detect 10 and 100 mbits/s capabilities to and from a remote device. setting the autonegotiation enable (aneg_en) bit in the mi serial port control register enables autonegotiation. appropriately setting the bits in the mi serial port autonegotiation advertisement register selects the advertised speed capability. autonegotiation functionality is described in more detail in section 2.2.11, link integrity and autonegotiation . 2.7.3 10/100 mbits/s indication the device can be programmed such that the operation speed (10 or 100 mbits/s) appears on the pled0n pin. to do this, appropriately set the programmable led output select bits in the mi serial port con?guration 2 register as described in table 2.9 . when the pled0n pin is pro- grammed to be speed detect output, it is asserted low when the device is con?gured for 100 mbit/s operation. the pled0n output has both pul- lup and pulldown driver transistors and a weak pullup resistor, so it can drive an led from either v dd or gnd and can also drive a digital input.
draft 6/5/00 jabber 2-47 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.8 jabber a jabber condition occurs in 10 mbits/s mode when the transmit packet exceeds a predetermined length. when jabber is detected, the tp transmit outputs are forced to the idle state, a collision is asserted, the jab register bit is set in the mi serial port status register, and the jab bit is set in the mi serial port status output register. to disable the jabber function, set the jabber disable bit (jab_dis) in the mi serial port con?guration 2 register the jabber function is disabled in the 100 mbits/s mode. 2.9 automatic jam this section describes automatic jam operation for both 100 and 10 mbits/s operation. 2.9.1 100 mbits/s jam the L80223 has an automatic jam feature that causes the device to automatically transmit a jam packet if receive activity is detected. if automatic jam is enabled, the following jam packet is transmitted on tpo when the rx_en/jamn pin is asserted low and receive activity is detected on the tp inputs (expressed in 5b code words): /j/k/5/5/5/5/5/5/5/5/5/5/5/5/5/d/h/h/h/h/h/h/h/h/t/r/ this automatic jam feature is enabled when the rx_en/jam pin is programmed to be a jam input. to con?gure the rx_en/jamn pin as a jamn input, set the r/j_cfg bit in the mi serial port con?guration 2 register. 2.9.2 10 mbits/s jam the jam feature for the 10 mbits/s mode is identical to that of the 100 mbits/s mode except that the jam packet transmitted on tpo consists of the standard 62-bit preamble (alternating 1s and 0s) followed with the sfd pattern (0b11), which is then followed with 32 bits of alternating 1s and 0s.
draft 6/5/00 2-48 functional description copyright ? 2000 by lsi logic corporation. all rights reserved. 2.10 reset the device is reset when: 1. v dd is applied to the device, or 2. the reset bit (rst) is set in the mi serial port control register, or 3. the resetn pin is asserted (low). when reset occurs because of (1) or (2), an internal power-on reset pulse is generated that resets all internal circuits, forces the mi serial port bits to their default values, and latches in new values for the mi address. after the power-on reset pulse has ?nished, the reset bit (rst) in the mi serial port control register is cleared and the device is ready for normal operation. when reset is initiated because of (3), the same procedure occurs except the device stays in the reset state as long as the resetn pin is held low. the resetn pin has an internal pullup to v dd . the device is guaranteed to be ready for normal operation 50 ms after the reset sequence is initiated. 2.11 powerdown to powerdown the L80223, set the powerdown bit (pdn) in the mi serial port control register. in powerdown mode, the tp outputs are in a high-impedance state, all functions are disabled except the mi serial port, and the power consumption is reduced to a minimum. the device is guaranteed to be ready for normal operation 500 ms after the pdn bit is cleared.
draft 6/5/00 receive polarity correction 2-49 copyright ? 2000 by lsi logic corporation. all rights reserved. 2.12 receive polarity correction in 10 mbits/s mode, the polarity of the signal on the tp receive input is continuously monitored. if either three consecutive link pulses or one soi pulse indicates incorrect polarity on the tp receive input, the polarity is internally determined to be incorrect. in this case, the reverse polarity detect bit (rpol) is set in the mi serial port status output register. the device automatically corrects for the reverse polarity condition, provided the autopolarity feature is not disabled. to disable autopolarity, set the autopolarity disable bit (apol_dis) in the mi serial port con?guration 2 register. no polarity detection or correction is needed in the 100 mbits/s mode.
draft 6/5/00 2-50 functional description copyright ? 2000 by lsi logic corporation. all rights reserved.
L80223 10base-t/100base-tx/fx ethernet phy 3-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 chapter 3 signal descriptions this chapter describes the device signals. it contains the following sections: section 3.1, media interface signals section 3.2, controller interface signals (mii) section 3.3, management interface section 3.4, miscellaneous signals section 3.5, leds section 3.6, power supply figure 3.1 is a logic diagram for the device.
draft 6/5/00 3-2 signal descriptions copyright ? 2000 by lsi logic corporation. all rights reserved. figure 3.1 device logic diagram 3.1 media interface signals rext transmit current set i/o an external resistor connected between the rext pin and gnd sets the output current for the tp and fx transmit outputs. sd/fxdisn i fx signal detect input/fx interface disable when this pin is not tied to gnd, the fx interface is enabled and this pin becomes an ecl signal detect input. media interface oscin tx_en controller interface management interface mdc mdio pled3n/mda3n pled2n/mda2n pled1n/mda1n leds/ col resetn miscellaneous 10/100 mbit/s ethernet physical layer device (phy) (mii) tpi+/fxo- tpi-/fxo+ tpo+/fxi- tpo-/fxi+ tx_er/txd4 txd[3:0] rxd[3:0] rx_en/jamn rx_clk tx_clk rx_dv pled0n/mda0n rx_er/rxd4 mi address crs speed rext dplx aneg rptr sd/fxdisn sd_thr mdintn/mda4n pled4n pled5n L80223
draft 6/5/00 media interface signals 3-3 copyright ? 2000 by lsi logic corporation. all rights reserved. the voltage on sd_thr determines the trip point for this ecl input. when this pin is tied to gnd, the fx interface is disabled and the tp interface is enabled. sd_thr signal detect input threshold level set i the voltage on this pin determines the ecl threshold level (trip point) for the sd input pin so that the device can directly interface to both 3.3 v and 5 v ?ber optic transceivers. typically, this pin is either tied to gnd (for 3.3 v operation) or to an external voltage divider (for 5 v operation). tpo+/fxi- twisted-pair transmit output (positive), or fiber optic receive input (negative) i/o the tpo+/fxi- pin is shared for the twisted-pair and ?ber optic signals. it functions as the positive signal in the twisted-pair output or the negative signal in the ?ber optic input. tpo-/fxi+ twisted-pair transmit output (negative), or fiber optic receive input (positive) i/o the tpo-/fxi+ pin is shared for the twisted-pair and ?ber optic signals. it functions as the negative signal in the twisted-pair output or the positive signal in the ?ber optic input. tpi+/fxo- twisted-pair receive input (positive), or fiber optic transmit output (negative) i/o the tpi+/fxo- pin is shared for the twisted-pair and ?ber optic signals. it functions as the positive signal in the twisted-pair input or the negative signal in the ?ber optic output. tpi-/fxo+ twisted-pair receive input (negative), or fiber optic output (positive) i/o the tpi-/fxo+ pin is shared for the twisted-pair and ?ber optic signals. it functions as the negative signal in the twisted-pair input or the positive signal in the ?ber optic output.
draft 6/5/00 3-4 signal descriptions copyright ? 2000 by lsi logic corporation. all rights reserved. 3.2 controller interface signals (mii) crs carrier sense output o the crs output is asserted high when valid data is detected on the receive tp inputs. crs is clocked out on the falling edge of rx_clk. oscin clock oscillator input i there must be either a 25 mhz crystal between this pin and gnd or a 25 mhz clock applied to this pin. tx_clk output is generated from this input. rx_clk receive clock output o receive data on rxd, rx_dv, and rx_er is clocked out to an external controller on the falling edge of rx_clk. rxd[3:0] receive data output o rxd[3:0] contain receive nibble data from the tp input, and they are clocked out on the falling edge of rx_clk. rx_dv receive data valid output o rx_dv is asserted high when valid decoded data is present on the rxd outputs. rx_dv is clocked out on the falling edge of rx_clk. rx_en/jamn receive enable input i the function of this pin is con?gured through the r/j con?guration select bit (r/j_cfg) in the mi serial port con?guration 1 register. when r/j_cfg is set, the pin is con?gured as jamn; when it is cleared, the pin functions as rx_en rx_en function: when rx_en is high, all of the receive outputs (rx_clk, rxd[3:0], rx_dv, rx_er, col) are enabled. when rx_en is low, the outputs are in a high-impedance state. jamn function: when jamn is high, a jam packet is transmitted when receive activity is detected. when jamn is low, no jam packet is transmitted. rxer/rxd4 receive error output/fifth receive data output o the rxer/rxd4 output is asserted high when a coding error or other speci?ed errors are detected on the receive
draft 6/5/00 management interface 3-5 copyright ? 2000 by lsi logic corporation. all rights reserved. twisted-pair inputs. the signal is clocked out on the falling edge of rx_clk. if the device is placed in the bypass 4b5b decoder mode (the byp_enc bit is set in the mi serial port con?gura- tion 1 register), this pin is recon?gured to be the ?fth rxd receive data output, rxd4. tx_clk transmit clock output o transmit data from the controller on txd, tx_en, and tx_er is clocked in on the rising edge of tx_clk and oscin. txd[3:0] transmit data input i txd[3:0] contain input nibble data to be transmitted on the tp outputs, and they are clocked in on the rising edge of tx_clk and oscin when tx_en is asserted. tx_en transmit enable input i tx_en must be asserted high to indicate that data on txd and tx_er is valid. tx_er is clocked in on the ris- ing edge of tx_clk and oscin. tx_er/txd4 transmit error input/fifth transmit data input i the txer pin, when asserted, causes a special pattern to be transmitted on the twisted-pair outputs in place of normal data, and it is clocked in on the rising edge of tx_clk when tx_en is asserted. if the device is placed in the bypass 4b5b encoder mode (the byp_enc bit is set in the mi serial port con?gura- tion 1 register), this pin is recon?gured to be the ?fth txd transmit data input, txd4. 3.3 management interface mdc mi clock i the mdc clock shifts serial data for the internal registers into and out of the mdio pin on its rising edge. mdintn/mda4n management interface interrupt output/ management interface address input pullup o.d. i/o this pin is an interrupt output and is asserted low whenever there is a change in certain mi serial port
draft 6/5/00 3-6 signal descriptions copyright ? 2000 by lsi logic corporation. all rights reserved. register bits. the pin is deasserted after all changed bits have been read out. during powerup or reset, this pin is high impedance and the state of the pin is latched in as the physical device address mda4 for the mi serial port. mdio mi data i/o this bidirectional pin contains serial data for the internal registers. the data on this pin is clocked in and out of the device on the rising edge of mdc. 3.4 miscellaneous signals aneg autonegotiation input i this pin control autonegotiation operation. col collision output o col is asserted high when a collision between transmit and receive data is detected. dplx full/half duplex select input i when the aneg pin is low, the dplx pin selects half/full duplex operation. when the aneg pin is high, the dplx pin is ignored and the half/full duplex operation is controlled from the aneg pin meaning high autonegotiation is on. autonegotiation enable is controlled from the aneg_en bit, 10/100 mbits/s operation is controlled from the speed bit, and half/full duplex operation is controlled from the dplx bit. low autonegotiation is off. 10/100 mbits/s operation is controlled from the speed pin and half/full duplex operation is controlled from the dplx pin. duplx pin meaning high full duplex operation low half duplex operation
draft 6/5/00 leds 3-7 copyright ? 2000 by lsi logic corporation. all rights reserved. duplex mode select bit (dplx) in the mi serial port con- trol register or the autonegotiation outcome. nc no connect 13 of the pins are not connected. resetn hardware reset input pullup i rptr repeater mode enable input i the rptr pin controls the device repeater operation. speed speed select input i when the aneg pin is low, the speed pin selects 10/100 mbits/s operation. when the aneg pin is high, this pin is ignored and the speed is determined from the speed select bit (speed) in the mi serial port control register or the autonegotiation outcome. 3.5 leds pled5n receive led output pullup o.d. o the function of this pin is to be a receive activity detect output. the pin can drive an led from v dd . resetn pin meaning high normal low device is in a reset state. rptr pin meaning high repeater mode enabled low normal operation speed pin meaning high 100 mbits/s operation low 10 mbits/s operation pled5n pin function high no receive activity low receive packet occurred (held low for 100 ms)
draft 6/5/00 3-8 signal descriptions copyright ? 2000 by lsi logic corporation. all rights reserved. pled4n transmit led output pullup o.d. o the function of this pin is to be a transmit activity detect output. the pin can drive an led from v dd . pled3n/mda3n programmable led output/mi address bit pullup o.d. i/o the default function of this pin is to be a 100 mbits/s link detect output. this pin can also be programmed through the mi serial port to indicate other events or be user con- trolled. this pin can drive an led from v dd . when programmed as a 100 mbits/s link detect output (default): during powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical device address mda3n for the mi serial port. pled2n/mda2n programmable led output/mi address bit pullup o.d. i/o the default function of this pin is to be an activity detect output. this pin can also be programmed through the mi serial port to indicate other events or be user controlled. this pin can drive an led from v dd . when programmed as an activity detect output (default): during powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical device address mda2n for the mi serial port. pled4n pin function high no transmit activity low transmit packet occurred (held low for 100 ms) pled3n/mda3n pin function high no link detect low 100 mbits/s link detected pled2n/mda2n pin function high no activity low transmit or receive packet occurred (held low for 100 ms)
draft 6/5/00 leds 3-9 copyright ? 2000 by lsi logic corporation. all rights reserved. pled1n/mda1n programmable led output/mi address bit pullup o.d. i/o the default function of this pin is to be a full duplex detect output. this pin can also be programmed through the mi serial port to indicate other events or be user controlled. this pin can drive an led from both v dd and gnd. when programmed as full duplex detect output (default): during powerup or reset, this pin is high-impedance and the level on this pin is latched in as the physical address device address mda1n for the mi serial port. pled0n/mda0n programmable led output/mi address bit pullup o.d. i/o the default function of this pin is to be a 10 mbits/s link detect output. this pin can also be programmed through the mi serial port to indicate other events or be user controlled. this pin can drive an led from both v dd and gnd. when programmed as 10 mbits/s link detect output (default): during powerup or reset, this pin is high-impedance and the value on this pin is latched in as the address mda0n for the mi serial port. pled1n/mda1n pin function high half-duplex low full-duplex pled0n/mda0n pin function high no detect low 10 mbits/s link detected
draft 6/5/00 3-10 signal descriptions copyright ? 2000 by lsi logic corporation. all rights reserved. 3.6 power supply gnd ground i there are six ground pins. they must be connected to ground (0 volts). v dd positive supply i there are six v dd pins. they must be connected to 3.3 5% volts.
L80223 10base-t/100base-tx/fx ethernet phy 4-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 chapter 4 registers this chapter contains a description of the registers accessed over the management interface (mi) serial interface. it contains the following sections: section 4.1, bit types section 4.2, mi serial port register summary section 4.3, registers for further information about the operation of the mi serial interface, see chapter 5, management interface .
draft 6/5/00 4-2 registers copyright ? 2000 by lsi logic corporation. all rights reserved. 4.1 bit types because the serial port is bidirectional (capable of both read and write operations), there are many types of bits. the following bit type de?nitions are summarized in table 4.1 : write bits (w) are inputs during a write cycle and are high impedance during a read cycle read bits (r) are outputs during a read cycle and high impedance during a write cycle read/write bits (r/w) are actually write bits that can be read out during a read cycle r/wsc bits are r/w bits that are self-clearing after a set period of time or after a speci?c event has completed r/ll bits are read bits that latch themselves when they go low, and they stay low until read. after they are read, they are reset high. r/lh bits are the same as r/ll bits, except that they latch high. r/lt are read bits that latch themselves whenever they make a transition or change value, and they stay latched until they are read. after r/lt bits are read, they are updated to their current value. table 4.1 mi register bit type de?nition symbol name de?nition write cycle read cycle w write input no operation, hi-z r read no operation, hi-z output r/w read/write input output r/wsc read/write, self-clearing input output (clears itself after the operation completes)
draft 6/5/00 bit types 4-3 copyright ? 2000 by lsi logic corporation. all rights reserved. r/ll read/latching low no operation, hi-z output when the bit goes low, it is latched. when the bit is read, it is updated. r/lh read/latching high no operation, hi-z output when the bit goes high, it is latched. when the bit is read, it is updated. r/lt read/latching on transition no operation, hi-z output when the bit transitions, the bit is latched. when the bit is read, the bit is updated. table 4.1 mi register bit type de?nition (cont.) symbol name de?nition write cycle read cycle
draft 6/5/00 4-4 registers copyright ? 2000 by lsi logic corporation. all rights reserved. 4.2 mi serial port register summary the following tables summarize the device registers accessible through the mi serial port. control register (register 0) C status register (register 1) C phy id #1 register (register 2) C phy id #2 register (register 3) C 15 14 13 12 11 10 9 8 rst lpbk speed aneg_en pdn mii_dis aneg_rst dplx 76 0 coltst reserved 15 14 13 12 11 10 8 cap_t4 cap_txf cap_txh cap_tf cap_th reserved 76543210 reserved cap_supr aneg_ack rem_flt cap_aneg link jab exreg 15 14 13 12 11 10 9 8 oui3 oui4 oui5 oui6 oui7 oui8 oui9 oui10 76543210 oui11 oui12 oui13 oui14 oui15 oui16 oui17 oui18 15 14 13 12 11 10 9 8 oui19 oui20 oui21 oui22 oui23 oui24 part5 part4 76543210 part3 part2 part1 part0 rev3 rev2 rev1 rev0
draft 6/5/00 mi serial port register summary 4-5 copyright ? 2000 by lsi logic corporation. all rights reserved. autonegotiation advertisement register (register 4) C autonegotiation remote end capability register (register 5) C con?guration 1 register (register 16) C con?guration 2 register (register 17) C status output register (register 18) C 15 14 13 12 10 9 8 np ack rf reserved t4 tx_fdx 7654 10 tx_hdx 10_fdx 10_hdx reserved csma 15 14 13 12 10 9 8 np ack rf reserved t4 tx_fdx 7654 10 tx_hdx 10_fdx 10_hdx reserved csma 15 14 13 12 11 10 9 8 link_dis xmt_dis xmt_pdn txen_crs byp_enc byp_scr unscr_dis eqlzr 76 5 21 0 cable rlvl0 tlvl[3:0] trf[1:0] 15 14 13 12 11 10 9 8 pled3_1 pled3_0 pled2_1 pled2_0 pled1_1 pled1_0 pled0_1 pled0_0 76 54321 0 led_def1 led_def0 apol_dis jab_dis mreg int_mdio r/j_cfg 0 15 14 13 12 11 10 9 8 int link_fail loss_sync cwrd ssd esd rpol jab 76 5 0 spd_det dplx_det reserved
draft 6/5/00 4-6 registers copyright ? 2000 by lsi logic corporation. all rights reserved. mask register (register 19) C reserved register (register 20) C 15 14 13 12 11 10 9 8 mask_int mask_lnk_ fail mask_loss _sync mask_cwrd mask_ssd mask_esd mask_rpol mask_jab 76 5 4 3 0 mask_spd_ det mask_dplx _det fxlvl[1:0] reserved 15 14 13 12 11 10 9 8 reserved 76 5 0 reserved
draft 6/5/00 registers 4-7 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3 registers this section contains a description of each of the bits in each register. 4.3.1 control register (register 0) the default value for this register is 0x3000. rst reset r/wsc 15 lpbk loopback enable r/w 14 speed speed select r/w 13 aneg_en autonegotiation enable r/w 12 15 14 13 12 11 10 9 8 rst lpbk speed aneg_en pdn mii_dis aneg_rst dplx 76 0 coltst reserved rst bit meaning 1 reset. the bit is bit self-clearing in less than or equal to 200 m s after reset ?nishes. 0 normal (default) lpbk bit meaning 1 loopback mode enabled 0 normal (default) speed bit 1 meaning 1 100 mbit/s (100base-tx) (default) 0 10 mbit/s (10base-t) 1. the speed bit is effective only when autonegotiation is off, and the bit can be overridden with the assertion of the speed pin. aneg_en bit 1 meaning 1 1 = autonegotiation enabled (default) 0 0 = disabled
draft 6/5/00 4-8 registers copyright ? 2000 by lsi logic corporation. all rights reserved. pdn power down enable r/w 11 mii_dis mii interface disable r/w 10 aneg_rst autonegotiation reset r/wsc 9 dplx duplex mode select r/w 8 coltst collision test enable r/w 7 r reserved r [6:0] these bits are reserved and must be remain at the default value of 0x00 for proper device operation. 1. the aneg_en pin can be overridden with the assertion of the aneg pin. pdn bit meaning 1 power down 0 normal (default) mii_dis 1 bit 0 mii interface disable 1 normal (default) 1. if mda[3:0]n is not read as 0b1111 at reset time, the mii_dis default value is changed to 0. aneg_rst bit 1 restart autonegotiation process. the bit is self-clearing after reset is ?nished 0 normal (default) dplx bit 1 1 full-duplex 0 half-duplex (default) 1. this bit is effective only when autonegotia- tion is off, and the bit can be overridden with the assertion of the dplx pin. coltst bit 1 collision test enabled 0 normal (default)
draft 6/5/00 registers 4-9 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.2 status register (register 1) the default value of this register is 0x7809. cap_t4 100base-t4 capable r 15 cap_txf 100base-tx full duplex capable r 14 cap_txh 100base-tx half duplex capable r 13 cap_tf 10base-t full duplex capable r 12 cap_th 10base-t half duplex capable r 11 r reserved r [10:7] these bits are reserved and must be remain at the default value of 0x0 for proper device operation 15 14 13 12 11 10 8 cap_t4 cap_txf cap_txh cap_tf cap_th reserved 76543210 reserved cap_supr aneg_ack rem_flt cap_aneg link jab exreg cap_t4 bit meaning 1 capable of 100base-t4 operation 0 not capable of 100base-t4 operation (default) cap_txf bit meaning 1 capable of 100base-tx full-duplex (default) 0 not capable of 100base-tx full-duplex cap_txh bit meaning 1 capable of 100base-tx half-duplex (default) 0 not capable of 100base-tx half-duplex cap_tf bit meaning 1 capable of 10base-t full-duplex (default) 0 not capable of 10base-t full-duplex cap_th bit meaning 1 capable of 10base-t half duplex (default) 0 not capable of 10base-t half duplex
draft 6/5/00 4-10 registers copyright ? 2000 by lsi logic corporation. all rights reserved. cap_supr mi preamble suppression capable r 6 aneg_ack autonegotiation acknowledgment r 5 rem_flt remote fault detect r/lh 4 cap_aneg autonegotiation capable r 3 link link status r/ll 2 jab jabber detect r/lh 1 cap_supr bit meaning 1 capable of accepting mi frames with preamble suppression 0 not capable of accepting mi frames with preamble suppression (default) aneg_ack bit meaning 1 autonegotiation acknowledgment process complete 0 autonegotiation not complete (default) rem_flt bit meaning 1 remote fault detect. the rem_flt bit is set when the remote fault (rf) bit is set in the autonegotiation remote end capability register. 0 no remote fault (default) cap_aneg bit meaning 1 capable of autonegotiation (default) 0 not capable of autonegotiation link bit meaning 1 link detected (same as the lnk_fail bit inverted). see section 4.3.9, status output register (register 18), page 4-23 ) 0 link not detected (default) jab bit meaning 1 jabber detected (same as the jab bit in section 4.3.9, status output register (register 18), page 4-23 ) 0 normal (default)
draft 6/5/00 registers 4-11 copyright ? 2000 by lsi logic corporation. all rights reserved. exreg extended register capable r 0 4.3.3 phy id 1 register (register 2) oui[3:18] company id, bits 3C18 r [15:0] oui[3:18] in this register and oui[19:24] of the phy id 2 register make up the lsi oui, whose default value is 0x00.a07d. the table below shows the default bit posi- tions for the entire oui ?eld: exreg bit meaning 1 extended registers exist (default) 0 extended registers do not exist 15 14 13 12 11 10 9 8 oui3 oui4 oui5 oui6 oui7 oui8 oui9 oui10 76543210 oui11 oui12 oui13 oui14 oui15 oui16 oui17 oui18 bit default value hex value oiu24 0 0x7 oiu23 1 oiu22 1 oiu21 1 oiu20 1 0xd oiu19 1 oiu18 0 oiu17 1 oiu16 1 0xa oiu15 0 oiu14 1 oiu13 0 oiu12 0 0x0 oiu11 0 oiu10 0 oiu9 0
draft 6/5/00 4-12 registers copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.4 phy id 2 register (register 3) oui[19:24] company id, bits 19C24 r [15:10] oui[19:24] in this register and oui[3:18] of the phy id 1 register make up the lsi oui, whose default value is 0x00.a07d. see the table in the phy id 1 description for a description of the entire oui ?eld. part[5:0] manufacturers part number r [9:4] the default value for this ?eld is 0x04. the table below shows the default bit positions for the part[5:0] ?eld: rev[3:0] manufacturers revision number r [3:0] the default value for this ?eld is 0x0. oiu8 0 0x0 oiu7 0 oiu6 0 oiu5 0 oiu4 0 0x0 oui3 0 15 14 13 12 11 10 9 8 oui19 oui20 oui21 oui22 oui23 oui24 part5 part4 76543210 part3 part2 part1 part0 rev3 rev2 rev1 rev0 bit default value hex value bit default value hex value part[5] 0 0x0 part[4] 0 part[3] 0 0x4 part[2] 1 part[1] 0 part[0] 0
draft 6/5/00 registers 4-13 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.5 autonegotiation advertisement register (register 4) the default value for this register is 0x01e1. np next page enable r 15 ack acknowledge r 14 rf remote fault r/w 13 r reserved r/w[12:10] these bits are reserved and must be remain at the default value of 0b00 for proper device operation t4 100base-t4 capable r/w 9 15 14 13 12 10 9 8 np ack rf reserved t4 tx_fdx 7654 10 tx_hdx 10_fdx 10_hdx reserved csma np bit meaning 1 next page 1 0 no next page (default) 1. next page is not currently supported ack bit meaning 1 received autonegotiation word recognized 0 not recognized (default) rf bit meaning 1 autonegotiation remote fault detect 0 no remote fault detect (default) t4 bit meaning 1 capable of 100base-t4 operation 0 not capable (default)
draft 6/5/00 4-14 registers copyright ? 2000 by lsi logic corporation. all rights reserved. tx_fdx 100base-tx full duplex capable r/w 8 tx_hdx 100base-tx half duplex capable r/w 7 10_fdx 10base-tx full duplex capable r/w 6 10_hdx 10base-tx half duplex capable r/w 5 r reserved r/w [4:1] these bits are reserved and must be remain at the default value of 0x0 for proper device operation csma csma 802.3 capable r/w 0 tx_fdx bit meaning 1 capable of 100base-tx full duplex operation (default) 0 not capable tx_hdx bit meaning 1 capable of 100base-tx half-duplex operation (default) 0 not capable 10_fdx bit meaning 1 capable of 10base-t full-duplex operation (default) 0 not capable 10_hdx bit meaning 1 capable of 10base-t half-duplex operation (default) 0 not capable csma bit meaning 1 capable of 802.3 csma 1 operation (default) 0 not capable 1. carrier-sense, multiple-access
draft 6/5/00 registers 4-15 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.6 autonegotiation remote end capability register (register 5) the default value for this register is 0x0000. np next page enable r 15 ack acknowledge r 14 rf remote fault r 13 r reserved r [12:10] these bits are reserved and must be remain at the default value of 0b00 for proper device operation t4 100base-t4 capable r 9 15 14 13 12 10 9 8 np ack rf reserved t4 tx_fdx 7654 10 tx_hdx 10_fdx 10_hdx reserved csma np bit meaning 1 next page exists 0 no next page (default) ack bit meaning 1 received autonegotiation word recognized 0 not recognized (default) rf bit meaning 1 autonegotiation remote fault detect 0 no remote fault (default) t4 bit meaning 1 capable of 100base-t4 operation 0 not capable (default)
draft 6/5/00 4-16 registers copyright ? 2000 by lsi logic corporation. all rights reserved. tx_fdx 100base-tx full duplex capable r 8 tx_hdx 100base-tx half duplex capable r 7 10_fdx 10base-tx full duplex capable r 6 10_hdx 10base-tx half duplex capable r 5 r reserved r [4:1] these bits are reserved and must be remain at the default value of 0x0 for proper device operation csma csma 802.3 capable r 0 tx_fdx bit meaning 1 capable of 100base-tx full duplex operation 0 not capable (default) tx_hdx bit meaning 1 capable of 100base-tx half duplex operation 0 not capable (default) 10_fdx bit meaning 1 capable of 10base-t full duplex operation 0 not capable (default) 10_hdx bit meaning 1 capable of 10base-t half duplex operation 0 not capable (default) csma bit meaning 1 capable of 802.3 csma 1 operation 0 not capable (default) 1. carrier-sense, multiple-access
draft 6/5/00 registers 4-17 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.7 con?guration 1 register (register 16) the default value for this register is 0x0022. lnk_dis link disable r/w 15 xmt_dis device reset r/wsc 14 xmt_pdn tp transmit powerdown r/w 13 txen_crs tx_en to crs loopback disable r/w 12 15 14 13 12 11 10 9 8 lnk_dis xmt_dis xmt_pdn txen_crs byp_enc byp_scr unscr_dis eqlzr 76543210 cable rlvl0 tlvl3 tlvl2 tlvl1 tlvl0 trf1 trf0 lnk_dis bit meaning 1 receive link detect function disable (force link pass) 0 normal (default) xmt_dis bit meaning 1 tp transmitter disabled 0 normal (default) xmt_pdn bit meaning 1 tp transmitter powered down 0 normal (default) txen_crs bit meaning 1 tx_en to crs loopback disabled 0 loopback enabled (default)
draft 6/5/00 4-18 registers copyright ? 2000 by lsi logic corporation. all rights reserved. byp_enc bypass encoder/decoder select r/w 11 byp_scr bypass scrambler/descrambler select r/w 10 unscr_dis unscrambled idle reception disabled r/w 9 eqlzr receive equalizer select r/w 8 cable cable type select r/w 7 rlvl0 receive input level adjust r/w 6 byp_enc bit meaning 1 bypass 4b/5b encoder/decoder 0 normal (default) byp_scr bit meaning 1 bypass scrambler/descrambler 0 normal (default) unscr_dis bit meaning 1 disable autonegotiation with devices that transmit unscrambled idle on powerup and various instances 0 enable autonegotiation with devices that transmit unscrambled idle on powerup and various instances (default) eqlzr bit meaning 1 receive equalizer disabled (set to zero length) 0 receive equalizer on (for 100 mbits/s mode only) (default) cable bit meaning 1 stp (150 ohm) 0 utp (100 ohm) (default) rlvl0 bit meaning 1 receive squelch levels reduced by 4.5 db 0 normal (default)
draft 6/5/00 registers 4-19 copyright ? 2000 by lsi logic corporation. all rights reserved. tlvl[3:0] transmit output level adjust r/w [5:2] the transmit output current level is derived from an inter- nal reference voltage and the external resistor on the rext pin. the transmit level can be adjusted with either the external resistor on the rext pin, or the four trans- mit level adjust bits (tlvl[3:0]), as shown. the adjust- ment range is approximately -14% to +16% in 2% steps. trf[1:0] transmit rise/fall time adjust r/w [1:0] tlvl[3:0] bits gain 0b0000 1.16 0b0001 1.14 0b0010 1.12 0b0011 1.10 0b0100 1.08 0b0101 1.06 0b0110 1.04 0b0111 1.02 0b1000 (default) 1.00 0b1001 0.98 0b1010 0.96 0b1011 0.94 0b1100 0.92 0b1101 0.90 0b1110 0.88 0b1111 0.86 trf[1:0] bits adjustment 0b11 -0.25 ns 0b10 (default) +0.0 ns 0b01 +.25 ns 0b00 +.50 ns
draft 6/5/00 4-20 registers copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.8 con?guration 2 register (register 17) the default value for this register is 0xff00. pled3_[1:0]n programmable led 3 output select r/w [15:14] pled2_[1:0]n programmable led 2 output select r/w [13:12] 15 14 13 12 11 10 9 8 pled3_1n pled3_0n pled2_1n pled2_0n pled1_1n pled1_0n pled0_1n pled0_0n 7 43210 led_def1 led_def0 apol_dis jab_dis mreg reserved pled3_1n pled3_0n meaning 1 1 normal (pled3n pin state is determined from the led_def[1:0] bits (default is link100). 0b11 is the default for these bits 1 0 led tied to pled3n blinks (toggles 100 ms low, then 100 ms high) 0 1 led tied to pled3n on steady (pled3n output low) 0 0 led tied to pled3n off steady (pled3n output high) pled2_1n pled2_0n meaning 1 1 normal (pled2n pin state is determined from the led_def[1:0] bits (default is activity). 0b11 is the default for these bits 1 0 led tied to pled2n blinks (toggles 100 ms low, then 100 ms high) 0 1 led tied to pled2n on steady (pled2n output low) 0 0 led tied to pled2n off steady (pled2n output high)
draft 6/5/00 registers 4-21 copyright ? 2000 by lsi logic corporation. all rights reserved. pled1_[1:0]n programmable led 1 output select r/w [11:10] pled0_[1:0]n programmable led 0 output select r/w [9:8] led_def_[1:0] led normal function select r/w [7:6] see table 2.8 on page 2-32 for these bit de?nitions. apol_dis autopolarity disable r 5 jab_dis jabber disable r 4 pled1_1n pled1_0n meaning 1 1 normal (pled1n pin state is determined from the led_def[1:0] bits (default is full-duplex). 0b11 is the default for these bits 1 0 led tied to pled1n blinks (toggles 100 ms low, then 100 ms high) 0 1 led tied to pled1n on steady (pled1n output low) 0 0 led tied to pled1n off steady (pled1n output high) pled0_1n pled0_0n meaning 1 1 normal (pled0n pin state is determined from the led_def[1:0] bits (default is link 10). b11 is the default for these bits 1 0 led tied to pled0n blinks (toggles 100 ms low, then 100 ms high) 0 1 led tied to pled0n on steady (pled0n output low) 0 0 led tied to pled0n off steady (pled0n output high) apol_dis bit meaning 1 autopolarity correction disabled 0 normal (default) jab_dis bit meaning 1 jabber disabled 0 jabber enabled (default)
draft 6/5/00 4-22 registers copyright ? 2000 by lsi logic corporation. all rights reserved. mreg multiple register access enable r 3 int_mdio interrupt scheme select r/w 2 r/j_cfg r/j con?guration select r/w 1 r reserved r/w 0 this bit is reserved and must be remain at the default value of 0x0 for proper device operation. mreg bit meaning 1 multiple register access enabled 0 no multiple register access (default) int_mdio bit meaning 1 interrupt signaled with mdio pulse during idle 0 interrupt not signaled on mdio (default) r/j_cfg bit meaning 1 rx_en/jamn pin is con?gured to be jamn 0 rx_en/jamn pin is con?gured to be rx_en (default)
draft 6/5/00 registers 4-23 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.9 status output register (register 18) the default value for this register is 0x0080. int interrupt detect r 15 lnk_fail link fail detect r/lt 14 loss_sync descrambler loss of synchronization detect r/lt 13 cwrd codeword error r/lt 12 ssd start of stream error r/lt 11 15 8 int lnk_fail loss_sync cwrd ssd esd rpol jab 75 0 spd_det dplx_det reserved int bit meaning 1 interrupt bit(s) have changed since last read operation 0 no change (default) lnk_fail bit meaning 1 link not detected 0 normal (default) loss_sync bit meaning 1 descrambler has lost sync 0 normal (default) cwrd bit meaning 1 invalid 4b5b code detected on receive data 0 normal (default) ssd bit meaning 1 no start of stream delimiter detected on receive data 0 normal (default)
draft 6/5/00 4-24 registers copyright ? 2000 by lsi logic corporation. all rights reserved. esd end of stream error r/lt 10 rpol reversed polarity detect r/lt 9 jab jabber detect r/lt 8 spd_det 100/10 speed detect r/lt 7 dplx_det duplex detect r/lt 6 r reserved r [5:0] these bits are reserved and must be remain at the default value of 0x0 for proper device operation. esd bit meaning 1 no end of stream delimiter detected on receive data 0 normal (default) rpol bit meaning 1 reversed polarity detect 0 normal (default) jab bit meaning 1 jabber detected 0 normal (default) spd_det bit meaning 1 device in 100base-tx mode (default) 0 device in 10base-t mode dplx_det bit meaning 1 device in full duplex mode 0 device in half duplex mode (default)
draft 6/5/00 registers 4-25 copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.10 interrupt mask register (register 19) the default value for this register is 0xffc0. mask_ int r/w 15 interrupt mask - interrupt detect mask_ lnk_fail r/w 14 interrupt mask - link fail detect mask_ loss_sync r/w 13 interrupt mask - descrambler loss of sync detect mask_ cwrd r/w 12 interrupt mask - codeword error 15 14 13 12 11 10 9 8 mask_int mask_lnk_ fail mask_loss _sync mask_cwrd mask_ssd mask_esd mask_rpol mask_jab 76543 0 mask_ spd_det mask_ dplx_det fxlvl1 fxlvl0 reserved mask_int bit meaning 1 mask interrupt when int bit = 1 in register 18 (default) 0 no interrupt mask mask_lnk_fail bit meaning 1 mask interrupt for lnk_fail bit in register 18 (default) 0 no mask mask_loss_sync bit meaning 1 mask interrupt for loss_sync bit in register 18 (default) 0 no mask mask_cwrd bit meaning 1 mask interrupt for cwrd bit in register 18 (default) 0 no mask
draft 6/5/00 4-26 registers copyright ? 2000 by lsi logic corporation. all rights reserved. mask_ ssd interrupt mask - start of stream error r/w 11 mask_ esd interrupt mask - end of stream error r/w 10 mask_ rpol r/w 9 interrupt mask - reverse polarity detect mask_ jab r/w 8 interrupt mask - jabber detect mask_ spd_det r/w 7 interrupt mask - 10/100 speed detect mask_ssd bit meaning 1 mask interrupt for ssd bit in register 18 (default) 0 no mask mask_esd bit meaning 1 mask interrupt for esd bit in register 18 (default) 0 no mask mask_rpol bit meaning 1 mask interrupt for rpol bit in register 18 (default) 0 no mask mask_jab bit meaning 1 mask interrupt for jab bit in register 18 (default) 0 no mask mask_spd_det bit meaning 1 mask interrupt for spd_det bit in register 18 (default) 0 no mask
draft 6/5/00 registers 4-27 copyright ? 2000 by lsi logic corporation. all rights reserved. mask_ dplx_det r/w 6 interrupt mask - 10/100 duplex detect fxlvl[1:0] fiber transmit level adjust r/w [5:4] r reserved r/w [3:0] these bits are reserved and must be remain at the default value of 0 for proper device operation mask_dplx_det bit meaning 1 mask interrupt for dplx_det bit in register 18 (default) 0 no mask fxlvl[1:0] bits adjustment 0b11 1.30 0b10 1.15 0b01 0.85 0b00 (default) 1.00
draft 6/5/00 4-28 registers copyright ? 2000 by lsi logic corporation. all rights reserved. 4.3.11 reserved register (register 20) the default value for this register is 0x0000. r reserved r/w [15:0] these bits are reserved and must be remain at the default value of 0 for proper device operation. 15 8 reserved 7 0 reserved
L80223 10base-t/100base-tx/fx ethernet phy 5-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 chapter 5 management interface this chapter describes the management interface, over which the internal device registers are accessed. it contains the following sections: section 5.1, signal description section 5.2, general operation section 5.3, multiple register access section 5.4, frame structure section 5.5, register structure section 5.6, interrupts the management interface, referred to as the mi serial port, is an eight- pin bidirectional link through which the internal device registers are accessed. the internal register bits control the con?guration and capabilities of the device, and re?ect device status. the mi serial port provides access to 11 internal registers and meets all ieee 802.3 speci?cations for the management interface.
draft 6/5/00 5-2 management interface copyright ? 2000 by lsi logic corporation. all rights reserved. 5.1 signal description the mi serial port has eight pins: mdc: serial shift clock input pin mdio: bidirectional data pin mdintn: interrupt pin mda[4:0]n: physical address pins the mda[4:0]n pins con?gure the device for a particular address, from 0b0000 to 0b1111, such that 16 devices can exist in the same address domain, and each be addressed separately over the mi serial port. when an mi read or write cycle occurs, the device compares the internally inverted and latched state of the mda[4:0]n pins to the phyad[4:0] address bits of the mi frame. if the states compare, the device knows it is being addressed. the mda[4:0]n inputs share the same pins as the mdintn and pled[3:0]n outputs, respectively. at powerup or reset, the pled[3:0]n and mdintn output drivers are 3-stated for an interval called the power-on reset time. during the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the mi serial port physical device addresses.
draft 6/5/00 general operation 5-3 copyright ? 2000 by lsi logic corporation. all rights reserved. 5.2 general operation the mi serial port is idle when at least 32 continuous ones are detected on the bi-directional mdio data pin and remains idle as long as continuous ones are detected. during idle, the mdio output driver is in the high-impedance state. when the mi serial port is in the idle state, a 0b01 pattern on the mdio pin initiates a serial shift cycle. control and address bits are clocked into mdio on the next 14 rising edges of mdc (the mdio output driver is still in a high-impedance state). if the multiple register access mode is not enabled, data is either shifted in or out on mdio on the next 16 rising edges of mdc, depending on whether a write or read cycle was selected with the read and write operation bits. after the 32 mdc cycles have been completed: one complete register has been read or written the serial shift process is halted data is latched into the device the mdio output driver goes into a high-impedance state. another serial shift cycle cannot be initiated until the idle condition is detected again (at least 32 continuous ones). figure 5.1 shows a timing diagram for a mi serial port cycle.
draft 6/5/00 5-4 management interface rev. letter copyright ? 2000 by lsi logic corporation. all rights reserved. figure 5.1 mi serial port frame timing diagram write cycle mdc mdio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 01 01 st op p4 p3 phyad p2 p1 p0 r4 r3 regad r2 r1 r0 10 ta d15 d14 d13 d12 d11 data d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 write bits phy clocks in data on rising edges of mdc with t s = 10 ns minimum and t h = 10 ns minimum read cycle mdc mdio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 01 10 st op p4 p3 phyad p2 p1 p0 r4 r3 regad r2 r1 r0 z0 ta d15 d14 d13 d12 d11 data d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 write bits phy clocks in data on rising edges of mdc with read bits phy clocks out data on rising edges of mdc with t s = 10 ns minimum, and t h = 10 ns minimum t d = 20 ns maximum note: st = start bits, op = operation bits (read or write), phad = phy address, regad = register address, ta = turnaround bits for more detailed timing information on t h ,t h , and t h , see chapter 6, speci?cations.
draft 6/5/00 multiple register access 5-5 copyright ? 2000 by lsi logic corporation. all rights reserved. 5.3 multiple register access multiple registers can be accessed on a single mi serial port access cycle with the multiple register access feature. setting the multiple register access enable (mreg) bit in the mi serial port con?guration 2 register enables the multiple register access feature. when the phyad[4:0] bits in the mi frame match mda[4:0]n pins on the device and the regad[4:0] bits are set to 0b11111 during the ?rst 16 clock cycles, all 11 registers are accessed on the 176 rising edges of mdc (11 registers x 16 bits per register) that occur after the ?rst 16 mdc clock cycles of the mi serial port access cycle. there is no actual register residing at 0b1111, but this condition triggers the access of multiple registers. the registers (0, 1, 2, 3, 4, 5, 16, 17, 18, 19, and 20) are accessed in numerical order from 0 to 20. after all 192 mdc clocks (16 + 176) have been completed: all the registers have been read or written the serial shift process is halted data is latched into the device mdio goes into a high-impedance state. another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous ones) is detected.
draft 6/5/00 5-6 management interface copyright ? 2000 by lsi logic corporation. all rights reserved. 5.4 frame structure the structure of the serial port frame is shown in figure 5.2 and a timing diagram is shown in figure 5.1 . each serial port access cycle consists of 32 bits, exclusive of idle. the ?rst 16 bits of the serial port cycle are always write bits and are used for control and addressing. the last 16 bits are data that is written to or read from a data register. the ?rst two bits in figure 5.2 and figure 5.1 are start bits (st[1:0]) and must be written as a 0b01 for the serial port cycle to continue. the next two bits are the read and write bits, which determine whether a registers is being read or written. the next ?ve bits are the phy device address bits (phyad[4:0]), and they must match the inverted values latched from the mda[4:0]n pins during the power on reset time for access to continue. the next ?ve bits are register address select (regad[4:0]) bits, which select one of the 11 registers for access. the next two bits are turnaround (ta) bits, which are not actual register bits but provide the device extra time to switch the mdio pin function from a write pin to a read pin, if necessary. the ?nal 16 bits of the mi serial port cycle are written to or read from the speci?c data register that the register address bits (regad[4:0]) designate. figure 5.2 shows the mi frame structure. idle idle pattern w these bits are an idle pattern. the device does not initiate an mi cycle until it detects an idle pattern of at least 32 consecutive ones. st[1:0] start bits w when st[1:0] = 01, a mi serial port access cycle starts. read read select w when the read bit is 1, it designates a read cycle. write write select w when the write bit is 1, it designates a write cycle. figure 5.2 mi serial frame structure idle st[1:0] read write phyad[4:0] regad[4:0] ta[1:0] d[15:0]
draft 6/5/00 frame structure 5-7 copyright ? 2000 by lsi logic corporation. all rights reserved. phyad[4:0] physical device address w when the phyad[4:0] bits match the inverted latched value of the mda[3:0]n pins, the devices mi serial port is selected for operation. regad[4:0] register address w the regad[4:0] bits determine the speci?c register to access. ta[1:0] turnaround time r/w these bits provide some turnaround time for mdio to allow it to switch to a write input or read output, as needed. when read = 1, ta[1:0] = 0bz0; when write = 1, ta[1:0] = 0b10 . d[15:0] data r or w these 16 bits contain data to or from one of the registers selected with the register address bits regad[4:0].
draft 6/5/00 5-8 management interface copyright ? 2000 by lsi logic corporation. all rights reserved. 5.5 register structure the device has 11 16-bit registers. a map of the registers is shown in section 4.2, mi serial port register summary . see chapter 4, registers for a complete description of each register. the 11 registers consist of six registers that are de?ned by ieee 802.3 speci?cations (registers 0 to 5) and ?ve registers that are unique to the device (registers 16 through 20). table 5.1 gives a summary of the functions of each register. table 5.1 mi serial port register summary register name description 0 control register stores various con?guration bits 1 status register contains device capability and status output bits 2 phy id 1 contain an identi?cation code unique to the device 3 phy id 2 4 autonegotiation advertisement contains bits that control the operation of the autonegotiation algorithm 5 autonegotiation remote end capability contains bits that re?ect the autonegotiation capabilities of the link partners phy 16 con?guration 1 stores various con?guration bits 17 con?guration 2 stores various con?guration bits 18 channel status output contains status 19 mask contains interrupt mask bits 20 reserved reserved for factory use
draft 6/5/00 interrupts 5-9 copyright ? 2000 by lsi logic corporation. all rights reserved. 5.6 interrupts the device has hardware and software interrupt capability. certain output status bits (also referred to as interrupt bits) in the serial port trigger interrupts. the r/lt interrupt bits (bits [14:6]) in the channel status output register cause an interrupt when they transition provided they are not masked with the mask bits in the interrupt mask register. these interrupt bits stay latched until read. when all interrupt bits are read, the interrupt indication is removed and the interrupt bits that caused the interrupt are updated to their current value. setting the appropriate mask register bits in the interrupt mask register individually can mask and remove an interrupt bit as a source of interrupt. interrupt indication is done in three ways: mdintn pin: the mdintn pin is an active-low interrupt output indication. int bit: the int bit in the status output register, when set, indicates that one or more interrupt bits have changed since the register was last read. interrupt pulse on mdio: when the interrupt scheme select bit (int_mdio) is set in the con?guration 2 register, an interrupt is indicated with a low-going pulse on mdio when mdc is high and the serial port is in the idle state, as shown in the timing diagram in figure 5.3 . after the interrupt pulse, mdio goes back to the high- impedance state. if the interrupt occurs while the serial port is being accessed, the mdio interrupt pulse is delayed until one clock bit after the serial port access cycle has ended, as shown in figure 5.3
draft 6/5/00 5-10 management interface copyright ? 2000 by lsi logic corporation. all rights reserved. figure 5.3 mdio interrupt pulse internal interrupt mdc mdio mdio hi-z pulled high externally interrupt pulse mdio hi-z pulled high externally internal interrupt mdc mdio mdio hi-z pulled high externally interrupt pulse mdio hi-z pulled high externally b1 b0 last two bits of read cycle
L80223 10base-t/100base-tx/fx ethernet phy 6-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 chapter 6 speci?cations this chapter contains the complete electrical, timing, and mechanical speci?cations for the device. it contains the following sections: section 6.1, absolute maximum ratings section 6.2, electrical characteristics section 6.2.2, fx characteristics, transmit section 6.3, ac electrical characteristics section 6.4, led driver timing characteristics section 6.5, pinouts and package drawings section 6.6, mechanical drawing
draft 6/5/00 6-2 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.1 absolute maximum ratings table 6.1 shows the device absolute maximum ratings. these are limits which, if exceeded, could cause permanent damage to the device or affect device reliability. all voltages are speci?ed with respect to gnd unless otherwise speci?ed. table 6.1 absolute maximum ratings parameter range units v dd supply voltage - 0.3v to +4.0v v all inputs and outputs - 0.3v to 5.5v v package power dissipation 2.0 @ 70?c w storage temperature - 65 to +150 ?c temperature under bias - 10 to +80 ?c ?c lead temperature (soldering, 10 sec) 260 ?c body temperature (soldering, 30 sec) 220 ?c
draft 6/5/00 electrical characteristics 6-3 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.2 electrical characteristics table 6.2 lists the device dc electrical characteristics. unless otherwise noted, all test conditions are as follows: ta=0to+70?c v dd = 3.3 v 5% clock = 25 mhz + 0.01% rext = 10 k w 1%, no load table 6.2 dc characteristics limit sym parameter min typ max unit conditions vil input low voltage 0.8 volt all except oscin, mda[4:0]n sd/fxdisn, sd_thr v dd - 1.0 volt mda[4:0]n 1.5 volt oscin 0.45 volt sd/fxdisn (for fx disable), sd_thr (for 3.3v/5v select) vih input high voltage 2 volt all except oscin, mdan[4:0], sd/fxdisn, sd_thr v dd - 0.5 volt mda[4:0]n 2.3 volt oscin 0.85 volt sd/fxdisn (for fx disable), sd_thr (for 3.3 v/5 v select) iil input low current - 1 ua vin = gnd all except oscin, mda[4:0]n, resetn - 4 - 25 ua vin = gnd. mda[4:0]n - 12 - 120 ua vin = gnd. resetn - 150 ua vin = gnd. oscin
draft 6/5/00 6-4 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. iih input high current 1 ua vin = v dd . all except oscin, rptr 12 120 ua vin = v dd . rptr 150 ua vin = v dd . oscin vol output low voltage 0.4 volt iol = - 4 ma. all except pled[5:0]n 1 volt iol = - 10 ma. pled[5:0]n voh output high voltage v dd - 1.0 volt ioh = 4 ma. all except pled[5:0]n, mdintn 2.4 volt ioh = 4 ua. pled[5:2n], mdintn v dd - 1.0 volt ioh = 10 ma. pled[1:0]n cin input capacitance 5 pf i dd v dd supply current 120 ma transmitting, 100 mbits/s 140 ma transmitting, 10 mbits/s ignd gnd supply current 190 ma transmitting, 100 mbits/s 1 220 ma transmitting, 10 mbits/s 1 ipdn powerdown supply current 200 m a powerdown, either i dd or ignd 1. ignd includes current ?owing into gnd from the external resistors and transformer on tpo/fxo as shown in figure a.1 table 6.2 dc characteristics (cont.) limit sym parameter min typ max unit conditions
draft 6/5/00 electrical characteristics 6-5 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.2.1 twisted-pair dc characteristics unless otherwise noted, all test conditions for tp transmit and receive operations are as follows: ta=0to+70?c v dd = 3.3 v 5% clock = 25 mhz 0.01% rext = 10 k w 1%,no load tpo+/- loading is as shown in figure a.1 or equivalent 62.5/10 mhz square wave on tp+/- inputs in 100/10 mbits/s modes table 6.3 shows the twisted-pair characteristics for transmit operation. table 6.3 twisted pair characteristics (transmit ) sym parameter limit unit conditions min typ max tov tp differential output voltage 0.950 1.000 1.050 v pk 100 mbits/s, utp mode, 100 ohm load 1.165 1.225 1.285 v pk 100 mbits/s, stp mode, 150 ohm load 2.2 2.5 2.8 v pk 10 mbits/s, utp mode, 100 ohm load 2.694 3.062 3.429 v pk 10 mbits/s, stp mode, 150 ohm load tovs tp differential output voltage symmetry 98 102 % 100 mbits/s, ratio of positive and negative amplitude peaks on tpo torf tp differential output rise and fall time 3.0 5.0 ns 100 mbits/s trf[1:0] = 0b10 torfs tp differential output rise and fall time symmetry 0.5 ns 100 mbits/s, difference between rise and fall times on tpo todc tp differential output duty cycle distortion 0.25 ns 100 mbits/s, output data = 0101... nrz pattern unscrambled, measure at 50% points
draft 6/5/00 6-6 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. toj tp differential output jitter 1.4 ns 100 mbits/s, output data = scrambled /h/ too tp differential output overshoot 5.0 % 100 mbits/s tovt tp differential output voltage template see figure 2.4 10 mbits/s tsoi tp differential output soi voltage template see figure 2.8 10 mbits/s tlpt tp differential output link pulse voltage template see figure 2.6 10 mbits/s, nlp and flp toiv tp differential output idle voltage 50 mv 10 mbits/s. measured on secondary side of transformer in figure a.1 . toia tp output current 38 40 42 ma pk 100 mbits/s, utp with tlvl[3:0] = 0b1000 31.06 32.66 34.26 ma pk 100 mbits/s, stp with tlvl[3:0] = 0b1000 88 100 112 ma pk 10 mbits/s, utp with tlvl[3:0] = 0b1000 71.86 81.64 91.44 ma pk 10 mbits/s, stp with tlvl[3:0] = 0b1000 toir tp output current adjustment range 0.80 1.2 vdd = 3.3 v, adjustable with rext, relative to toia with rext = 10k 0.86 1.16 vdd = 3.3 v, adjustable with tlvl[3:0] see section a.4, tp transmit output current set, page a-7 , relative to value at tlvl[3:0] = 0b1000 table 6.3 twisted pair characteristics (transmit (cont.) ) sym parameter limit unit conditions min typ max
draft 6/5/00 electrical characteristics 6-7 copyright ? 2000 by lsi logic corporation. all rights reserved. tora tp output current tlvl step accuracy 50 % relative to ideal values in table 2.6 . table 2.6 values relative to output with tlvl[3:0] = 0b1000. tor tp output resistance 10 k ohm toc tp output capacitance 15 pf table 6.3 twisted pair characteristics (transmit (cont.) ) sym parameter limit unit conditions min typ max
draft 6/5/00 6-8 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. table 6.4 shows the twisted-pair characteristics for receive operation. table 6.4 twisted pair characteristics (receive ) sym parameter limit unit conditions min typ max rst tp input squelch threshold 166 500 mv pk 100 mbits/s, rlvl0 = 0 310 540 mv pk 10 mbits/s, rlvl0 = 0 60 200 mv pk 100 mbits/s, rlvl0 = 1 186 324 mvpk 10 mbits/s, rlvl0 = 1 rut tp input unsquelch threshold 100 300 mv pk 100 mbits/s, rlvl0 = 0 186 324 mv pk 10 mbits/s, rlvl0 = 0 20 90 mv pk 100 mbits/s, rlvl0 = 1 112 194 mvpk 10 mbits/s, rlvl0 = 1 rocv tp input open circuit voltage vdd - 2.4 0.2 volt voltage on either tpi+ or tpi - with respect to gnd. rcmr tp input common mode voltage range rocv 0.25 volt voltage on tpi with respect to gnd. rdr tp input differential voltage range vdd volt rir tp input resistance 5 k ohm ric tp input capacitance 10 pf
draft 6/5/00 electrical characteristics 6-9 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.2.2 fx characteristics, transmit unless otherwise noted, all test conditions for fx transmit and receive operations are as follows: ta = 0 to +70 c vdd=3.3 v 5% 25 mhz 0.01% rext=10 k 1%, no load fxo loading as shown in figure a.1 or equivalent 125 mhz square wave on fxi+/- and sd inputs table 6.5 shows the fx characteristics for transmit operation. table 6.5 fx characteristics, transmit sym parameter limit unit conditions min typ max fovh fxo output voltage, high vdd - 1.020 vdd - 0.880 v single-ended, measure fxo relative to gnd fovl fxo output voltage, low vdd - 1.810 vdd - 1.620 v single-ended, measure fxo relative to gnd foia fxo output current 12 20 ma pk foir fxo output current adjustment range 0.85 1.15 vdd = 3.3 v, adjustable with rext, relative to foia with rext = 10 k 0.85 1.30 vdd = 3.3 v, adjustable with flvl[1:0], relative to value at flvl[1:0] = 0b10 fora fxo output current tlvl step accuracy 0.50 % relative to ideal values in table 2.9 forf fxo differential output rise and fall time 1.3 ns
draft 6/5/00 6-10 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. forfs fxo differential output and fall time symmetry 0.5 ns difference between rise nd fall times on fxo+ fodc fxo differential output duty cycle distortion 0.25 ns output data = 0101... pattern measure at 50% points foj fxo differential output jitter 1.3 ns output data = /h/ for fxo output resistance 10 k ohm foc fxo output capacitance 10 pf table 6.5 fx characteristics, transmit sym parameter limit unit conditions min typ max
draft 6/5/00 electrical characteristics 6-11 copyright ? 2000 by lsi logic corporation. all rights reserved. table 6.6 shows the fx characteristics for receive operation. table 6.6 fx characteristics, receive sym parameter limit unit conditions min typ max fdiv fxi differential input voltage 0.150 v pk fcmr fxi input common mode voltage range 1.35 vdd - 0.80 v voltage on either fxi+ or fxi- with respect to gnd fsdih sd/fxdisn input high voltage vtrip - 50mv v when sd/fxdisn is used as a signal detect input, not as the fx disable input. vtrip = (vdd -1.3v) 10%. fsdil sd/fxdisn input low voltage vtrip - 50 mv v when sd/fxdisn is used as a signal detect input, not as the fx disable input. vtrip = (vdd - 1.3v) 10% fsdthr sd_thr input voltage vdd - 1.3v - 2% vdd - 1.3v vdd - 1.3v + 2% v when interfacing to 5 v ?ber transceivers. when interfacing to 3.3 v ?ber transceivers, sd_thr is tied to gnd. fir fxi , sd/fxdisn input resistance 5k ohm fic fx sd/fxdisn input capacitance 10 pf
draft 6/5/00 6-12 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3 ac electrical characteristics unless otherwise noted, all test conditions are as shown in table 6.7 . table 6.7 test conditions test condition parameter value temperature ta 0 to +70 c voltage v dd 3.3v 5% clock frequency 25 mhz 0.01% external resistor rext 10k 1%, no load input conditions (all inputs) tr, tf 10 ns, 20-80% points output loading tpo open-drain outputs all other digital outputs same as figure a.1 or equivalent 10 pf 1k pullup, 50 pf 25 pf measurement points tpo ,tpi all other inputs and outputs 0.0 v during data, 0.3 v at start/end of packet 1.4 v
draft 6/5/00 ac electrical characteristics 6-13 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3.1 25 mhz input/output clock timing characteristics figure 6.1 25 mhz output timing table 6.8 25 mhz input/output clock 1 sym parameter limit unit conditions min typ max t1 oscin period 39.996 40 40.004 ns clock applied to oscin t2 oscin high time 16 ns clock applied to oscin t3 oscin low time 16 ns clock applied to oscin t4 oscin to tx_clk delay 10 ns 100 mbits/s 20 ns 10 mbits/s 1. refer to figure 6.1 for timing diagram oscin t 1 t 2 t 3 tx_clk (100 mbits/s) t 4 t 4 t 4 tx_clk (10 mbits/s)
draft 6/5/00 6-14 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3.2 transmit timing characteristics table 6.9 shows the transmit ac timing parameters. see figure 6.2 and figure 6.3 for the 100 mbits/s and 10 mbits/s transmit timing diagrams. table 6.9 transmit timing sym parameter limit unit conditions min typ max t11 tx_clk period 39.996 40 40.004 ns 100 mbits/s 399.96 400 400.04 ns 10 mbits/s t12 tx_clk low time 16 20 24 ns 100 mbits/s 160 200 240 ns 10 mbits/s t13 tx_clk high time 16 20 24 ns 100 mbits/s 160 200 240 ns 10 mbits/s t14 tx_clk rise/fall time 10 ns t15 tx_en setup time 15 ns note 1 t16 tx_en hold time 0 ns t17 crs during transmit assert time 40 ns 100 mbits/s 400 ns 10 mbits/s t18 crs during transmit deassert time 160 ns 100 mbits/s 900 ns 10 mbits/s t19 txd setup time 15 ns note 1 t20 txd hold time 0 ns t21 tx_er setup time 15 ns note 1 t22 tx_er hold time 0 ns t23 transmit propagation delay 60 140 ns 100 mbits/s, mii 140 ns 100 mbits/s, fbi 600 ns 10 mbits/s t24 transmit output jitter 0.7 ns pk-pk 100 mbits/s 5.5 ns pk-pk 10 mbits/s t25 transmit soi pulse width to 0.3 v 250 ns 10 mbits/s t26 transmit soi pulse width to 40 mv 4500 ns 10 mbits/s (sheet 1 of 2)
draft 6/5/00 ac electrical characteristics 6-15 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.2 transmit timing - 100 mbits/s t27 pledn delay time 25 ms pledn programmed for activity t28 pledn pulse width 80 105 ms pledn programmed for activity 1. setup time measured with 5 pf loading on txc. additional leading will create a delay on txc rise time, which requires increased setup times. table 6.9 transmit timing (cont.) sym parameter limit unit conditions min typ max (sheet 2 of 2) n1 tx_clk tx_en txd[3:0] tpo n0 n2 t 15 t 19 t 27 t 28 t 11 t 16 pledn idle idle /j/k/ data /t/r/ idle t 23 t 24 crs t 13 t 12 t 14 t 14 t 18 t 17 n3 t 20 t 22 t 21 tx_er mii 100 mbits/s fbi 100 mbits/s same as mii 100 mbits except: 1. tx_er converted to txd4 2. rx_er converted to rxd4
draft 6/5/00 6-16 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.3 transmit timing - 10 mbits/s preamble preamble data soi data n1 tx_clk tx_en txd[3:0] tp0 n0 n2 t 15 t 19 t 27 t 28 t 11 t 16 pledn t 23 crs t 13 t 12 t 14 t 14 t 18 t 17 n3 t 20 t 24 t 26 t 25 mii 10 mbits/s
draft 6/5/00 ac electrical characteristics 6-17 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3.3 receive timing characteristics table 6.10 shows the receive ac timing parameters. see figure 6.4 through figure 6.8 for the receive timing diagrams. table 6.10 receive timing limit sym parameter min typ max unit conditions t31 start of packet to crs assert delay 200 ns 100 mbits/s, mii 200 ns 100 mbits/s, fbi 700 ns 10 mbits/s t32 end of packet to crs deassert delay 130 240 ns 100 mbits/s, mii 240 ns 100 mbits/s, fbi 600 ns 10 mbits/s. relative to start of soi pulse t33 start of packet to rx_dv assert delay 240 ns 100 mbits/s 3600 ns 10 mbits/s t34 end of packet to rx_dv deassert delay 280 ns 100 mbits/s 1000 ns 10 mbits/s. relative to start of soi pulse t37 rx_clk to rx_dv, rxd, rx_er delay - 8 8 ns 100 mbits/s - 80 80 ns 10 mbits/s t38 rx_clk high time 18 20 22 ns 100 mbits/s 180 200 600 ns 10 mbits/s t39 rx_clk low time 18 20 22 ns 100 mbits/s 180 200 600 ns 10 mbits/s t40 soi pulse minimum width required for idle detection 125 200 ns 10 mbits/s measure tpi from last zero cross to 0.3v point.
draft 6/5/00 6-18 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. t41 receive input jitter 3.0 ns pk - pk 100 mbits/s 13.5 ns pk - pk 10 mbits/s t43 pledn delay time 25 ms pledn programmed for activity t44 pledn pulse width 80 105 ms pledn programmed for activity t45 rx_clk, rxd, crc, rx_dv, rx_er output rise and fall times 10 ns t46 rx_en deassert to rcv mii output hi-z delay 40 ns t47 rx_en assert to rcv mii output active delay 40 ns table 6.10 receive timing (cont.) limit sym parameter min typ max unit conditions
draft 6/5/00 ac electrical characteristics 6-19 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.4 receive timing, start of packet - 100 mbits/s rx rx rx rx rx rx rx rx tx tx t 38 data t tpi +/- crs rx_clk rxd[3:0] r i t 32 iiiiiiiiiiiiii iiii data data data data data data data mii 100 mbits/s t 39 t 34 t 37 rx_dv fbi 100 mbits/s same as mii 100 mbits except: 1. tx_er converted to rxd4 2. rx_er converted to txd4
draft 6/5/00 6-20 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.5 receive timing, end of packet - 100 mbits/s rx rx rx rx rx rx rx rx tx tx t 38 data t tpi +/- crs rx_clk rxd[3:0] r i t 32 iiiiiiiiiiiiii iiii data data data data data data data mii 100 mbits/s t 39 t 34 t 37 rx_dv fbi 100 mbits/s same as mii 100 mbits except: 1. tx_er converted to rxd4 2. rx_er converted to txd4
draft 6/5/00 ac electrical characteristics 6-21 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.6 receive timing, start of packet - 10 mbits/s rx rx rx rx rx rx tx tx tx tx tx data tpi +/- crs rx_clk rxd[3:0] data t 37 data data t 41 t 31 data preamble t 43 rx_er t 44 preamble t 38 t 39 t 33 pledn rx_dv t 37 mii 10 mbits/s
draft 6/5/00 6-22 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.7 receive timing, end of packet - 10 mbits/s figure 6.8 rx_en timing tpi +/- crs rx_clk rx_dv data t 41 data soi t 32 t 40 t 38 t 37 data data data data data data rx rxd[3:0] rx rx rx rx rx rx rx tx tx t 39 t 34 data data data data mii 10 mbits/s rx_en rx_clk rxd[3:0] rx_dv rx_er col t 47 t 46
draft 6/5/00 ac electrical characteristics 6-23 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3.4 collision and jam timing characteristics table 6.11 shows the collision and jam timing parameters. see figure 6.9 through figure 6.14 for the associated timing diagrams. table 6.11 collision and jam timing limit sym parameter min typ max unit conditions t51 rcv packet start to col assert time 200 ns 100 mbits/s 700 ns 10 mbits/s t52 rcv packet stop to col deassert time 130 240 ns 100 mbits/s 300 ns 10 mbits/s t53 xmt packet start to col assert time 200 ns 100 mbits/s 700 ns 10 mbits/s t54 xmt packet stop to col deassert time 240 ns 100 mbits/s 300 ns 10 mbits/s t55 pledn delay time 25 ms pledn programmed for collision t56 pledn pulse width 80 105 ms pledn programmed for collision t57 collision test assert time 5120 ns t58 collision test deassert time 40 ns t59 crs assert to transmit jam packet start during jam 300 ns 100 mbits/s 800 ns 10 mbits/s t60 1 col rise and fall time 10 ns 1. timing not shown
draft 6/5/00 6-24 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.9 collision timing, receive 100 mbits/s figure 6.10 collision timing, receive 10 mbits/s tpo +/- tpi +/- col pledn mii 100 mbits/s i data data data data data data data data data data data data data i i i i j k data data data data t r i i t 51 t 52 t 56 t 55 fbi 100 mbits/s same as mii 100 mbits mii 100 mbits/s t 51 t 52 t 55 t 56 tpo +/- tpi +/- col pledn
draft 6/5/00 ac electrical characteristics 6-25 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.11 collision timing, transmit - 100 mbits/s figure 6.12 collision timing, transmit - 10 mbits/s figure 6.13 collision test timing tpo +/- tpi +/- col pledn mii 100 mbits/s i data data data data data data data data data data data data data i i i i j k data data data data t r i i t 53 t 54 t 56 t 55 same as mii 100 mbits fbi 100 mbits/s mii 100 mbits/s t 53 t 54 t 55 t 56 tpi +/- tpo +/- col pledn col tx_en t 58 t 57
draft 6/5/00 6-26 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.14 jam timing tpo +/- crs col mii 100 mbits/s i i j data data data data data data t 53 t 53 same as mii 100 mbits fbi 100 mbits/s jamn k data data data data data data i i i k jam t i i j i t 59 jam jam jam ri i t 54 tpo +/-
draft 6/5/00 ac electrical characteristics 6-27 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3.5 link pulse timing characteristics table 6.12 shows the link pulse ac timing parameters. see figure 6.15 and figure 6.16 for the link pulse timing diagrams. table 6.12 link pulse timing sym parameter limit unit condition min typ max t61 nlp transmit link pulse width see figure 2.7 ns t62 nlp transmit link pulse period 824ms t63 nlp receive link pulse width required for detection 50 ns t64 nlp receive link pulse minimum period required for detection 6 7 ms link_test_min t65 nlp receive link pulse maximum period required for detection 50 150 ms link_test_max t66 nlp receive link pulses required to exit link fail state 3 3 3 link pulses lc_max t67 flp transmit link pulse width 100 150 ns t68 flp transmit clock pulse to data pulse period 55.5 62.5 69.5 m s interval_timer t69 flp transmit clock pulse to clock pulse period 111 125 139 m s t70 flp transmit link pulse burst period 8 22 ms transmit_link_burst _timer t71 flp receive link pulse width required for detection 50 ns t72 flp receive link pulse minimum period required for clock pulse detection 525 m s ?p_test_min_timer
draft 6/5/00 6-28 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. t73 flp receive link pulse maximum period required for clock pulse detection 165 185 m s ?p_test_max_timer t74 flp receive link pulse minimum period required for data pulse detection 15 47 m s data_detect_min_ timer t75 flp receive link pulse maximum period required for data pulse detection 78 100 m s data_detect_max_ timer t76 flp receive link pulses required to detect valid flp burst 17 17 link pulses t77 flp receive link pulse burst minimum period required for detection 5 7 ms nlp_test_min_timer t78 flp receive link pulse burst maximum period required for detection 50 150 ms nlp_test_max_ timer t79 flp receive link pulses bursts required to detect autonegotiation capability 3 3 3 link pulse t80 flp receive acknowledge fail period 1200 1500 ms t81 flp transmit renegotiate link fail period 1200 1500 ms break_link_timer t82 nlp receive link pulse maximum period required for detection after flp negotiation has completed 750 1000 ms link_fail_inhibit_ timer table 6.12 link pulse timing (cont.) sym parameter limit unit condition min typ max
draft 6/5/00 ac electrical characteristics 6-29 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.15 nlp link pulse timing figure 6.16 flp link pulse timing tpo +/- tpi +/- pledn a. transmit nlp b. receive nlp t 61 t 64 t 63 t 65 t 66 t 62 tpi +/- t 78 t 77 t 79 pledn a. transmit flp and transmit flp burst clk data clk data clk data clk tpo +/- t 68 t 69 t 67 t 70 clk data clk data t 73 t 71 31.25 62.50 125.00 156.25 t 74 t 75 tpi +/- b. receive flp c. receive flp burst 93.75 t 72
draft 6/5/00 6-30 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.3.6 jabber timing characteristics table 6.13 shows the jabber ac timing parameters. see figure 6.17 for the jabber timing diagram. figure 6.17 jabber timing table 6.13 jabber timing sym parameter limit unit conditions min typ max t91 jabber activation delay time 50 100 ms 10 mbits/s t92 jabber deactivation delay time 250 750 ms 10 mbits/s tpo +/- txen crs col t 91 t 92 t 91 t 91 fbi 100 mbits/s mi 10 mbits/s not applicable mii 100 mbits/s not applicable
draft 6/5/00 led driver timing characteristics 6-31 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.4 led driver timing characteristics table 6.14 shows the jabber ac timing parameters. see figure 6.18 for the jabber timing diagram. figure 6.18 led driver timing table 6.14 led driver timing sym parameter limit unit conditions min typ max t96 pled[5:0]n on time 80 105 ms pled[5:0]n programmed to blink t97 pled[5:0]n off time 80 105 ms pled[5:0]n programmed to blink pled[5:0]n t 96 t 97
draft 6/5/00 6-32 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.4.1 mi serial port timing characteristics table 6.15 shows the mi serial port ac timing parameters. see figure 6.19 and figure 6.20 for the associated timing diagram. table 6.15 mi serial port timing sym parameter limit unit conditions min typ max t101 mdc high time 20 ns t102 mdc low time 20 ns t103 mdio setup time 10 ns write bits t104 mdio hold time 10 ns write bits t105 mdc to mdio delay 20 ns read bits t106 mdio hi-z to active delay 20 ns write-read bit transition t107 mdio active to hi-z delay 20 ns read-write bit transition t108 frame delimiter (idle) 32 clocks number of consecutive mdc clocks with mdio = 1 t109 end of frame to mdintn transition 100 ns t110 mdc to mdio interrupt pulse assert delay 100 ns t111 mdc to mdio interrupt pulse deassert delay 100 ns
draft 6/5/00 led driver timing characteristics 6-33 copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.19 mi serial port timing figure 6.20 mdio interrupt pulse timing mdio mdc (read) mdio (write) 0 st1 st0 regad0 ta1 ta0 d15 d1 d0 1 13141516 1730 31 t 103 t 104 t 103 t 106 ta 1 t 105 t 107 t 104 st1 st0 regad0 ta0 d15 d14 d0 t 101 t 102 mdintn t 109 internal t 110 mdc t 111 mdio interrupt signal
draft 6/5/00 6-34 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.5 pinouts and package drawings this section contains the alphabetical and numerical pin listings for the L80223 as well as its pinouts and package drawing. 6.5.1 pinouts table 6.16 and table 6.17 contain the list of L80223 signals. the ?rst table lists the signals by category and the second lists them by pin number. table 6.16 L80223 pin list (by signal category) pin name pin number description media interface rext 50 transmit current set sd/fxdisn 53 signal detect/fx interface disable sd_thr 51 signal detect input threshold level set tpi -/fxo+ 59 twisted pair receive input, negative/fiber pair transmit output, positive tpi+/fxo- 58 twisted pair receive input, positive/fiber pair transmit output, negative tpo-/fxi+ 55 twisted pair transmit output, negative/fiber pair transmit input, positive tpo+/fxi- 54 twisted pair transmit output, positive/fiber pair transmit input, negative controller interface crs 13 carrier sense output oscin 42 clock oscillator input rx_clk 26 receive clock output rx_dv 14 receive data valid output rx_en/jamn 27 receive enable input/jam input rx_er/rxd4 18 receive error output/fifth receive data bit output rxd0 22 receive data output. rxd1 21 receive data output.
draft 6/5/00 pinouts and package drawings 6-35 copyright ? 2000 by lsi logic corporation. all rights reserved. rxd2 20 receive data output. rxd3 19 receive data output tx_clk 34 transmit clock output tx_en 40 transmit enable input tx_er/txd4 39 transmit error input/fifth transmit data bit input txd0 35 transmit data input. txd1 36 transmit data input. txd2 37 transmit data input. txd3 38 transmit data input management interface (mi) mdc 10 management interface (mi) clock input mdio 11 management interface (mi) data input/output mdintn/mda4n 9 management interface (mi) data input/output pled0n/mda0n 61 programmable led output /management interface address input. pled1n/mda1n 62 programmable led output /management interface address input pled2n/mda2n 3 programmable led output /management interface address input pled3n/mda3n 4 programmable led output /management interface address input pled4n 2 programmable led output pled5n 63 programmable led output miscellaneous aneg 30 autonegotiation input col 12 collision output dplx 29 full/half duplex select input resetn 44 reset input rptr 24 repeater mode enable input speed 28 speed select input table 6.16 L80223 pin list (by signal category) (cont.) pin name pin number description
draft 6/5/00 6-36 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. power v dd 1 56 positive supply. 3.3v 5% volts v dd 257 v dd 37 v dd 48 v dd 525 v dd 632 ground gnd1 52 ground gnd2 60 gnd3 6 gnd4 41 gnd5 23 gnd6 31 no connection nc 1 no connection nc 5 nc 15 nc 16 nc 17 nc 33 nc 43 nc 45 nc 46 nc 47 nc 49 nc 48 nc 64 table 6.16 L80223 pin list (by signal category) (cont.) pin name pin number description
draft 6/5/00 pinouts and package drawings 6-37 copyright ? 2000 by lsi logic corporation. all rights reserved. . table 6.17 L80223 pin list (by pin number) pin number pin name description 1 nc no connection 2 pled4n programmable led output 3 pled2n/mda2n programmable led output /management interface address input 4 pled3n/mda3n programmable led output /management interface address input 5 nc no connect 6 gnd3 ground 7 vdd3 positive supply. 3.3v 5% volts 8 vdd4 positive supply. 3.3v 5% volts 9 mdintn/mda4n management interface (mi) data input/output 10 mdc management interface (mi) clock input 11 mdio management interface (mi) data input/output 12 col collision output 13 crs carrier sense output 14 rx_dv receive data valid output 15 nc no connect 16 nc no connect 17 nc no connect 18 rx_er/rxd4 receive error output/fifth receive data bit output 19 rxd3 receive data output 20 rxd2 receive data output. 21 rxd1 receive data output. 22 rxd0 receive data output. 23 gnd5 ground 24 rptr repeater mode enable input 25 vdd5 positive supply. 3.3v 5% volts 26 rx_clk receive clock output 27 rx_en/jamn receive enable input
draft 6/5/00 6-38 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 28 speed speed select input 29 dplx full/half duplex select input 30 aneg autonegotiation input 31 gnd6 ground 32 vdd6 positive supply. 3.3v 5% volts 33 nc no connect 34 tx_clk transmit clock output 35 txd0 transmit data input. 36 txd1 transmit data input. 37 txd2 transmit data input. 38 txd3 transmit data input 39 tx_er/txd4 transmit error input/fifth transmit data bit input 40 tx_en transmit enable input 41 gnd4 ground 42 oscin clock oscillator input 43 nc no connect 44 resetn reset input 45 nc no connect 46 nc no connect 47 nc no connect 48 nc no connect 49 nc no connect 50 rext transmit current set 51 sd_thr signal detect input threshold level set 52 gnd1 ground 53 sd/fxdisn signal detect/fx interface disable 54 tpo+/fxi- twisted pair transmit output, positive/fiber pair transmit input, negative table 6.17 L80223 pin list (by pin number) (cont.) pin number pin name description
draft 6/5/00 pinouts and package drawings 6-39 copyright ? 2000 by lsi logic corporation. all rights reserved. 55 tpo-/fxi+ twisted pair transmit output, negative/fiber pair transmit input, positive 56 vdd1 positive supply. 3.3v 5% volts 57 vdd2 positive supply. 3.3v 5% volts 58 tpi+/fxo- twisted pair receive input, positive/fiber pair transmit output, negative 59 tpi -/fxo+ twisted pair receive input, negative/fiber pair transmit output, positive 60 gnd2 ground 61 pled0n/mda0n programmable led output /management interface address input. 62 pled1n/mda1n programmable led output /management interface address input 63 pled5n programmable led output 64 nc no connect table 6.17 L80223 pin list (by pin number) (cont.) pin number pin name description
draft 6/5/00 6-40 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. 6.5.2 L80223 pin layout figure 6.21 shows the pin layout for the L80223 package. figure 6.21 L80223 64-pin lqfp, top view L80223 64-pin lqfp top view nc pled4n pled2n/mda2n pled3n/mda3n nc gnd3 vdd3 vdd4 mdintn/mda4n mdc mdio col crs rx_dv nc nc nc rx_er/rxd4 rxd3 rxd2 rxd1 rxd0 gnd5 rptr vdd5 rx_clk rx_en/jamn speed dplx aneg gnd6 vdd6 nc nc nc nc resetn nc oscin gnd4 tx_en tx_er/txd4 txd3 txd2 txd1 txd0 tx_clk nc nc pled5n pled1n/mda1n pled0n/mda0n gnd2 tpi - fxo + tpi + fxo - vdd2 vdd1 tpo - /fxi + tpo + /fxi - sd/fxdisn gnd1 sd_thr rext nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. nc pins are not connected.
draft 6/5/00 mechanical drawing 6-41 copyright ? 2000 by lsi logic corporation. all rights reserved. 6.6 mechanical drawing this section contains the mechanical drawing for the L80223 64-pin lqfp package.
draft 6/5/00 6-42 speci?cations copyright ? 2000 by lsi logic corporation. all rights reserved. figure 6.22 64-pin lqfp mechanical drawing impor tant: this drawing may not be the latest version. d e pin 1 e see detail b e1 b d1 a see detail a symbol b e ccc ddd d e l l1 r r1 a a1 a2 c d1 e1 @ @1 @2 dimensions 0.17 C 0.27 0.50 basic max. 0.08 max. 0.08 11.85 C 12.15 11.85 C 12.15 0.45 C 0.75 1.0 ref 0.08 C 0.20 min. 0.08 max. 1.60 0.05 C 0.15 1.292 C 1.508 0.09 C 0.20 9.90 C 10.10 9.90 C 10.10 0?C7? min. 0? 12? ccc c b ddd detail b l @2 @1 @ l1 note: 2. all dimensions are in millimeters. 3. dimensions do not include mold ?ash. maximum allowable ?ash is 0.25. 4. all leads are coplanar to a tolerance of 0.08 (ccc). bent leads to a tolerance of 0.08 (ddd). a2 a r dimension table r1 detail b a1
L80223 10base-t/100base-tx/fx ethernet phy a-1 copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 appendix a application information this chapter contains application information for the device. it contains the following sections: section a.1, example schematics section a.2, tp transmit interface section a.3, tp receive interface section a.4, tp transmit output current set section a.5, cable selection section a.6, transmitter droop section a.7, automatic jam section a.8, fx interface section a.9, mii controller interface section a.10, fbi controller interface section a.11, serial port section a.12, oscillator section a.13, led drivers section a.14, repeater applications section a.15, power supply decoupling a.1 example schematics a typical example schematic of the L80223 used in an network interface adapter card application is shown in figure a.1 ; a hub application is shown in figure a.2 ; and an external phy application is shown in figure a.3 .
draft 6/5/00 a-2 application information copyright ? 2000 by lsi logic corporation. all rights reserved. figure a.1 typical network interface adapter card schematic using the L80223 vdd [6:1] gnd [6:1] bus interface 6 rext 10 k w tpi + tpi - 1 2 4 5 7 8 3 6 rj45 75 75 1:1 0.01 tpo + tpo - 50 1% 50 1% lsi l80c300 or equivalent 10/100 mbits/s ethernet tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio mdintn L80223 controller system bus 2 kv 75 1:1 25 1% 25 1% 0.01 25 1% 75 1% optional resetn to system reset or float led 500 6x optional oscin 25 mhz 25 1% pled4n speed dplx aneg vdd or gnd pinstrap to rx_en/jamn optional pled5n pled3n pled2n pled1n pled0n
draft 6/5/00 example schematics a-3 copyright ? 2000 by lsi logic corporation. all rights reserved. figure a.2 typical switching port schematic using L80223 vdd [6:1] gnd [6:1] switch fabric rext 10 k w tpi + tpi - 1 2 4 5 7 8 3 6 rj45 75 75 1:1 0.01 tpo + tpo - 50 1% 50 1% lsi l84c300 tx_clk txd txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio L80223 2 kv 75 1:1 25 1% 25 1% 0.01 25 1% 75 1% resetn to system reset or float 25 1% oscin 25 mhz system clock 4 led 500 4x optional or equivalent l_ledn la_ledn fd_ledn cd_ledn 50k speed dplx aneg vdd or gnd pinstrap to 6 led 500 6x optional pled4n pled5n pled3n pled2n pled1n pled0n mdintn optional rx_en/jamn optional 10/100 mbits/s ethernet controller
draft 6/5/00 a-4 application information copyright ? 2000 by lsi logic corporation. all rights reserved. figure a.3 typical external phy schematic using L80223 vdd [6:1] gnd [6:1] rext 10 k w tpi + tpi - 1 2 4 5 7 8 3 6 rj45 75 75 1:1 0.01 tpo + tpo - 50 1% 24.9 1% mii connectors tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio L80223 2 kv 75 1:1 25 1% 25 1% 0.01 25 1% 75 1% resetn oscin 25 mhz 25 1% 50 1% 1.5 k w 5% optional system clock speed dplx aneg vdd or gnd pinstrap to mdintn optional rx_en/jamn optional 6 led 500 6x optional pled4n pled5n pled3n pled2n pled1n pled0n
draft 6/5/00 tp transmit interface a-5 copyright ? 2000 by lsi logic corporation. all rights reserved. a.2 tp transmit interface the interface between the tp outputs on tpo and the twisted pair cable is typically transformer coupled and terminated with the two resistors as shown in figure a.1 through figure a.3 . the transformer for the transmitter should have a winding ratio of 1:1 with a center tap on the primary winding tied to v dd , as shown in figure a.1 through figure a.3 . the speci?cations for the transformer are shown in table a.1 . sources for the transformer are listed in table a.2 . the transmit output must be terminated with two external termination resistors to meet the output impedance and return loss requirements of ieee 802.3. these two external resistors must be connected between v dd and each of the tpo outputs. their value should be chosen to provide the correct termination impedance when looking back through the transformer from the twisted-pair cable, as shown in figure a.1 table a.1 tp transformer speci?cation parameter speci?cation transmit receive turns ratio 1:1 ct 1:1 inductance, ( hmin) 350 350 leakage inductance, ( h) 0.05C0.15 0.0C0.2 capacitance (pf max) 15 15 dc resistance ( w max) 0.4 0.4 table a.2 tp transformer sources vendor part number pulse h1089, h1102 bel s558-5999-j9 halo tg22-3506nd tg110-s050n2
draft 6/5/00 a-6 application information copyright ? 2000 by lsi logic corporation. all rights reserved. through figure a.3 . the value of these two external termination resistors depends on the type of cable the device drives. refer to section a.5, cable selection, page a-8 for more details. to minimize common mode output noise and to aid in meeting radiated emissions requirements, it may be necessary to add a common mode choke on the transmit outputs as well as add common mode bundle termination. the quali?ed transformers mentioned in table a.2 all contain common mode chokes along with the transformers on both the transmit and receive sides, as shown in figure a.1 through figure a.3 . common mode bundle termination may be needed and can be achieved when the unused pairs in the rj45 connector are connected to chassis ground through 75 ohm resistors and a 0.01 m f capacitor, as shown in figure a.1 through figure a.3 . to minimize noise pickup into the transmit path in a system or on a pcb, the loading on tpo should be minimized and both outputs should always be loaded equally. a.3 tp receive interface receive data is typically transformer coupled into the receive inputs on tpi and terminated with external resistors as shown in figure a.1 through figure a.3 . the transformer for the receiver should have a winding ratio of 1:1, as shown in figure a.1 through figure a.3 . the speci?cations for this transformer are shown in table a.1 and sources for the transformer are listed in table a.2 . the receive input must be terminated with the correct termination impedance to meet the input impedance and return loss requirements of ieee 802.3. in addition, the receive tp inputs must be attenuated. both the termination and attenuation is accomplished with four external resistors in series across the tpi inputs, as shown in figure a.1 through figure a.3 . each resistor should be 25% of the total series resistance, and the total series resistance should be equal to the characteristic impedance of the cable (100 w for utp, 150 w for stp). it is also recommended that a 0.01 fcapacitor be placed between the center of the series resistor string and v dd to provide an ac ground for attenuating
draft 6/5/00 tp transmit output current set a-7 copyright ? 2000 by lsi logic corporation. all rights reserved. common mode signal at the input. this capacitor is also shown in figure a.1 through figure a.3 . to minimize common mode input noise and to aid in meeting susceptibility requirements, it may be necessary to add a common mode choke on the receive input as well as add common mode bundle termination. the quali?ed transformers mentioned in table a.2 all contain common mode chokes along with the transformers on both the transmit and receive sides, as shown in figure a.1 through figure a.3 . common mode bundle termination may be needed and can be achieved when the receive secondary center tap and the unused pairs in the rj45 connector are connected to chassis ground through 75 w resistors and a 0.01 fcapacitor, as shown in figure a.1 through figure a.3 . to minimize noise pickup into the receive path in a system or on a pcb, loading on tpi should be minimized and both inputs should be loaded equally. a.4 tp transmit output current set the tpo output current level is set with an external resistor connected between the rext pin and gnd. this output current is determined from the following equation, where r is the value of rext: i out = (10k/r) i ref where rext should typically be a 10 k w 1% resistor to meet ieee 802.3 speci?ed levels. once rext is set for the 100 mb its/ s and utp modes as shown by the equation above, i ref is then automatically changed inside the device when the 10 mb its/ s mode or utp120/stp150 modes are selected. ir ef = 40 ma (100 mbits/s, utp) = 32.6 ma (100 mbits/s, stp) = 100 ma (10 mbits/s, utp) = 81.6 ma (10 mbits/s, stp)
draft 6/5/00 a-8 application information copyright ? 2000 by lsi logic corporation. all rights reserved. keep rext as close to the rext and gnd pins as possible to reduce noise pickup into the transmitter. because the tp output is a current source, capacitive and inductive loading can reduce the output voltage from the ideal level. thus, in actual application, it might be necessary to adjust the value of the output current to compensate for external loading. one way to adjust the tp output level is to change the value of the external resistor connected to rext. a better way to adjust the tp output level is to use the transmit level adjust register bits (tlvl[3:0]) accessed through the mi serial port con?guration 1 register. these four bits can adjust the output level by - 14% to +16% in 2% steps as described in table 2.6 . a.5 cable selection the L80223 can drive two different cable types: 100 ohm unshielded twisted-pair, category 5, or 150 ohm shielded twisted-pair. the L80223 must be properly con?gured for the type of cable to meet the return loss speci?cations in ieee 802.3. this con?guration requires appropriately setting the cable type select (cable) bit in the mi serial port con?guration 1 register and setting the value of some external resistors, as described in table a.3 . the cable bit sets the output current level for the cable type. rterm in table a.3 is the value of the termination resistors needed to meet the level and return loss requirements. the value for rterm on the tpo outputs is for the two external termination resistors connected from v dd table a.3 cable con?guration cable type cable bit rterm (ohms) tpo tpi 100 ohm utp, cat. 5 utp 50 100 150 ohm stp stp 75 150
draft 6/5/00 transmitter droop a-9 copyright ? 2000 by lsi logic corporation. all rights reserved. to tpo .each value for rterm on the tpi inputs is for the sum of the four series resistors across tpi ,as shown in figure a.1 C figure a.3 . these resistors should be 1% tolerance. also note that some output level adjustment may be necessary due to parasitics as described in section a.4, tp transmit output current set, page a-7 . ieee 802.3 speci?es that 10base-t and 100base-tx operate over twisted-pair cable lengths of between 0C100 meters. the squelch levels can be reduced by 4.5 db if the receive input level adjust bit (rlvl0) is set in the mi serial port con?guration 1 register. this allows the L80223 to operate with up to 150 meters of twisted-pair cable. the equalizer is already designed to accommodate between 0C125 meters of cable. a.6 transmitter droop the ieee 802.3 speci?cation has a transmit output droop requirement for 100base-tx. because the L80223 tp output is a current source, it has no perceptible droop by itself. however, the inductance of the transformer added to the device transmitter output as shown in figure a.1 through figure a.3 causes droop to appear at the transmit interface to the tp wire. if the transformer connected to the L80223 outputs meets the requirements of table a.1 , the transmit interface to the tp cable then meets the ieee 802.3 droop requirements. a.7 automatic jam the L80223 has an automatic jam generation feature that automatically transmits a jam packet when receive activity is detected. this feature is primarily designed to give the user a means to easily implement half-duplex ?ow control. in a typical application, a watermark signal from a system fifo or memory is be tied directly to the jamn pin. when the system fifo is nearly full and more data is being received, the device automatically transmits a jam packet and creates a collision, which causes the far end device to back off, allowing time for the system fifo to empty itself.
draft 6/5/00 a-10 application information copyright ? 2000 by lsi logic corporation. all rights reserved. the jam generation feature requires that the rx_en/jamn pin be programmed for jam. to do this, set the r/j_cfg bit in the mi serial port con?guration 2 register.
draft 6/5/00 fx interface a-11 copyright ? 2000 by lsi logic corporation. all rights reserved. a.8 fx interface the fx interface has differential pecl inputs (fxi+/ - ) and outputs (fxo+/ - ) that are typically connected to an external ?ber optic transceiver. the fx interface outputs are designed to drive 100-ohm differential loads. the fx interface can be directly coupled to either 3.3 v or 5 v ?ber optic transceivers with minimum external components, as described in the following sections. a.8.1 connection to 3.3 v transceivers the schematic for a typical connection of the device to an external 3.3 v ?ber optic transceiver is shown in figure a.4 . the 70- and 173-ohm resistors on fxo+/ - are used for 100 ohm termination and for biasing the device fxo+/ - outputs to match the input range on the 3.3 v ?ber optic transceiver inputs. place these resistors as close as possible on the pcb to the ?ber optic transceiver inputs. in addition, keep the parasitic loading on fxo+ and fxo - to a minimum and matched as well as possible. the 127 and 83 ohm resistors on fxi+/ - and sd/fxdisn are used for 100-ohm termination and for biasing the 3.3 v ?ber optic transceiver outputs to match the input range on the device fx inputs. place these resistors as close as possible on the pcb to the device fx inputs. in addition, keep the parasitic loading on fxi+ and fxi - to a minimum and matched as well as possible. in the 3.3 v transceiver application, the sd_thr pin must be tied to gnd, as shown in figure a.4 . the sd_thr pin determines the sd/fxdisn internal buffer ecl trip level. the sd/fxdisn internal buffer trip level needs to be set to vdd - 1.3 v and must be referenced to the 3.3 v supply. connecting sd_thr to gnd causes the device to internally set the ecl trip point on the sd/fxdisn input to v dd - 1.3 and references it to the common 3.3 v supply.
draft 6/5/00 a-12 application information copyright ? 2000 by lsi logic corporation. all rights reserved. figure a.4 connection to 3.3 v fiber optic transceivers a.8.2 connection to 5 v transceivers the schematic for a typical connection of the device to an external 5 v transceiver is shown in figure a.5 . 3.3 v 70 w 173 w 3.3 v v dd 3.3 v 70 w 173 w 3.3 v 127 w 83 w 3.3 v 127 w 83 w 3.3 v 127 w 83 w 3.3 v v dd gnd fxo+ fxo - fxi + fxi - sd/fxdisn sd_thr rext txo+ txo - rx+ rx - signal detect output gnd L80223 phy 3.3 v fiber optic transceiver 10 k w fiber
draft 6/5/00 fx interface a-13 copyright ? 2000 by lsi logic corporation. all rights reserved. figure a.5 connection to 5 v fiber optic transceivers the 62- and 263-ohm resistors on fxo+/ - are used for 100-ohm termination and for biasing the 3.3 v device fxo+/ - outputs to match the input range on the 5v ?ber optic transceiver inputs. place these resistors as closely as possible on the pcb to the ?ber optic transceiver inputs. in addition, keep the parasitic loading on fxo+ and fxo - to a minimum and matched as well as possible. 5 v 62 w 263 w 3.3 v vdd 5 v 62 w 263 w 5 v 83 w 83 w 5 v 83 w 57 w 83 w 5 v vdd gnd fxo+ fxo - fxi + fxi - sd/fxdisn sd_thr rext tx+ tx - rx+ rx - signal detect output gnd L80223 phy 5 v fiber optic transceiver 10 k w fiber 57 w 83 w 83 w 57 w 5 v 15 k w 10 k w 5 v
draft 6/5/00 a-14 application information copyright ? 2000 by lsi logic corporation. all rights reserved. the 83-, 57-, and 68-ohm resistors on fxi+/ - and sd/fxdisn are used for 100-ohm termination and for biasing the 5v ?ber optic transceiver outputs to match the input range on the 3.3v device fx inputs. place these resistors as closely as possible on the pcb to the device fx inputs. in addition, keep the parasitic loading on fxi+ and fxi - to a minimum and matched as well as possible. in the 5 v transceiver application, the sd_thr pin needs to be tied to v dd - 1.3 v, which can be done with an external resistor divider as shown in figure a.5 . the voltage on the sd_thr pin determines the sd/fxdisn internal buffer ecl trip level. the sd/fxdisn internal buffer trip level needs to be set to vdd - 1.3 v and must be referenced to the ?ber optic transceiver 5 v supply. using a resistor divider from the ?ber optic transceiver 5 v supply to generate the voltage for the sd_thr pin references the sd/fxdisn ecl trip level to the transceiver 5 v supply. this allows the device sd/fxdisn internal buffer ecl trip level to track the supply variations of the ?ber optic transceiver, allowing direct connection of the ?ber optic transceiver signal detect output to the device sd/fxdisn input, as shown in figure a.5 . a.8.3 disabling the fx interface connecting the sd/fxdisn pin to gnd disables the fx interface. when the fx interface is disabled, the tp interface is enabled, and vice versa.
draft 6/5/00 mii controller interface a-15 copyright ? 2000 by lsi logic corporation. all rights reserved. a.9 mii controller interface the mii controller interface allows the L80223 to connect to any external ethernet controller without any glue logic, provided the external ethernet controller has an mii interface that complies with ieee 802.3, as shown in figure a.1 through figure a.3 . a.9.1 clocks standard ethernet controllers with an mii use tx_clk to clock data in on txd[3:0]. tx_clk is speci?ed in ieee 802.3 and on the L80223 to be an output. if a non-standard controller or other digital device is used to interface to the L80223, there might be a need to clock txd[3:0] into the L80223 on the edges of an external master clock. the master clock, in this case, would be an input to the L80223. to do this, use oscin as the master clock input. because oscin generates tx_clk inside the L80223, data on txd[3:0] can be clocked into the L80223 on edges of output clock tx_clk or input clock oscin. in the case where oscin is used as the input clock, a crystal is no longer needed on oscin, and tx_clk can be left open or used for some other purpose. a.9.2 output drive the digital outputs on the L80223 controller signals meet the mii driver characteristics speci?ed in ieee 802.3 and shown in figure a.6 if external 24.9 w 1% termination resistors are added. these termination resistors are only needed if the outputs must drive an mii cable or other transmission line type load, such as in the external phy application shown in figure a.3 . if the L80223 is used in embedded applications, such as adapter cards and switching hubs (see figure a.1 and figure a.2 ), these termination resistors are not needed.
draft 6/5/00 a-16 application information copyright ? 2000 by lsi logic corporation. all rights reserved. figure a.6 mii output driver characteristics a.9.3 mii disable setting the mii disable bit (mii_dis) in the mi serial port control register places the mii outputs in the high-impedance state and the disables the mii inputs. when this bit is set to the disable state, the tp outputs are also disabled and transmission is inhibited. the default value of this bit when the device powers up or is reset is dependent on the physical device address. if the device address latched into mda[4:0] at reset is 0b11111, it is assumed that the device is being used in applications where there maybe more than one device sharing the mii bus, such as in the use of external phys or adapter cards. in this case, the device powers up with the mii interface disabled. if the device address latched into mda[4:0] at reset is not 0b11111, it is assumed that the device is being used in application where it is the only device on the mii bus, such voh vol loh lol rol min = 40 ohm v 3 i 3 v 4 i 4 v 2 i 2 v 1 i 1 v dd rol min = 40 ohm i C v i 1 , C v 1 i 2 , C v 2 i 3 , C v 3 i 4 , C v 4 i (ma) - 20 - 4 4 43 v (volts) 1.10 2.40 0.40 3.05
draft 6/5/00 fbi controller interface a-17 copyright ? 2000 by lsi logic corporation. all rights reserved. as in the use of hubs, so the device powers up with the mii interface enabled. a.9.4 receive output enable the receive output enable pin, rx_en, forces the receive and collision mii/fbi outputs into the high-impedance state. more speci?cally, when rx_en is deasserted, the rx_clk, rxd[3:0], rx_dv, rx_er, and col pins are placed in a high-impedance state. rx_en can be used to wire or the outputs of many L80223 devices in multiport applications where only one device may be receiving at a time, such as in a repeater application. monitoring the crs pin from each individual port enables the repeater to assert rx_en only to that L80223 device that is receiving data. the method reduces, by eight per device, the number of pins and pcb traces a repeater core ic requires. clear the r/j con?guration select bit (r/j_cfg) in the mi serial port con?guration 2 register to enable the rx_en function. when this bit is cleared, the rx_en/jamn pin becomes rx_en. a.10 fbi controller interface the fbi (five bit interface) controller interface has the same characteristics as that of the mii except that the data path is ?ve bits wide instead of 4 bits wide. the ?ve bit wide data path is automatically enabled when the 4b5b encoder is bypassed. because the encoder/decoder is bypassed, the fbi is used primarily for repeaters or other applications where the full phy is not needed. for more details about the fbi, see section a.14, repeater applications, page a-22 .
draft 6/5/00 a-18 application information copyright ? 2000 by lsi logic corporation. all rights reserved. a.11 serial port the L80223 uses an mi serial port to access the device registers. any external device that has a ieee 802.3 compliant mi interface can connect directly to the L80223 without any glue logic, as shown in figure a.1 through figure a.3 . as described earlier, the mi serial port consists of eight signals: mdc, mdio, mdintn, and mda[4:0]n. however, only two signals, mdc and mdio, are needed to shift data in and out. mda[4:0]n are not needed, but are provided for convenience only. note that the mda[4:0]n addresses are inverted inside the L80223 before going to the mi serial port block. this means that the mdan[4:0] pins would have to be pin strapped to 0b11111 externally to successfully match the mi physical address of 0b0000 on the phyad[4:0] bits internally. a.11.1 polling and interrupt the device status bits can be monitored in one of two ways: polling the serial port, or responding to interrupts the polling method reads the registers at regular intervals and compares the status bits to their previous values to determine any changes. to make polling simpler, all the registers can be accessed in a single read or write cycle. to do this, set the register address bits regad[4:0] to 0b11111 and add enough clocks to read out all the bits (provided the multiple register access feature has been enabled). the interrupt feature detects changes in the status output bits without register polling. when the device asserts an interrupt, it indicates that one or more of the status output bits has changed since the last read cycle. there are three interrupt output indicators on the device: mdintn pin assertion interrupt pulse on mdio int bit set in the mi serial port status output register.
draft 6/5/00 serial port a-19 copyright ? 2000 by lsi logic corporation. all rights reserved. an external device can use the interrupt indications to initiate a read cycle. when an interrupt is detected, the individual registers (or multiple registers) can be read out and the status bits compared against their previous values to determine any changes. after the interrupt bits have been read out, the interrupt signals are automatically deasserted. a mask register bit exists for every status output bit in the mi serial port interrupt mask register so that the interrupt bits can be individually programmed for each application. a.11.2 multiple register access if the mi serial port needs to be constantly polled in order to monitor changes in status output bits, or if it is desired that all registers be read or written in a single serial port access cycle, multiple register access mode can be used. multiple register access allows access to all registers in a single mi serial port access cycle. when multiple register access is enabled, all the registers are read or written when the register address regad[4:0] = 0b11111. this eliminates the need to read or write registers individually. multiple register access mode is normally disabled. to enable it, set the multiple register access enable (mreg) bit in the mi serial port con?guration 2 register. a.11.3 serial port addressing tying the mda[4:0]n pins to the desired value selects the device address for the mi serial port. mda[4:0]n share the same pins as the led outputs, as shown in figure a.7 a. at powerup or reset, the output drivers are 3-stated for an interval called the power-on reset time. during the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the mi serial port address. the led outputs are open-drain with internal pullup to v dd . if an led is to be connected on an led output, an led and resistor are tied to v dd as shown in figure a.6 b. if a high address is desired, the led to v dd automatically makes the latched address value a high. if a low value for the address is desired, a 50 k w resistor to gnd must be added as shown in figure a.6 b. if no leds are needed on the led outputs, the selection of addresses can be done as shown in figure a.6 c. if a high address is desired, the pin should be left ?oating and the internal pullup pulls the pin high
draft 6/5/00 a-20 application information copyright ? 2000 by lsi logic corporation. all rights reserved. during power-on reset time and latches in a high address value. if a low address is desired, the led and mdintn output pins should be tied either directly to gnd or through an optional 50 k w resistor to gnd. the led or mdintn outputs should always be tied through a 50 k w resistor to gnd since they have both pullup and pulldown capability. the optional 50k resistor also allows the mdintn and pled[3:0] pins to be used as digital outputs under normal conditions. figure a.7 serial device port address selection led 500 a. output driver/input address correspondence mda4n mda3n mda2n mda1n b. setting address with leds high led 500 low 50k c. setting address without leds high low 50k float mda0n pled1n pled2n pled3n mdintn pled0n pled1n pled2n pled3n mdintn pled0n pled1n pled2n pled3n mdintn pled0n pled1n pled2n pled3n mdintn pled0n pled1n pled2n pled3n mdintn pled0n
draft 6/5/00 oscillator a-21 copyright ? 2000 by lsi logic corporation. all rights reserved. a.12 oscillator the L80223 requires a 25 mhz reference frequency for internal signal generation. this 25 mhz reference frequency can be generated from an external 25 mhz crystal connected between oscin and gnd or from applying an external 25 mhz clock to oscin. if the crystal oscillator is used, it needs only a crystal; no other external capacitors or other components are required. the crystal must have the characteristics shown in table a.4 . the crystal must be placed as close as possible to the oscin and gnd pins so that parasitics on oscin are kept to a minimum. a.13 led drivers the led outputs can all drive leds tied to v dd as shown in figure a.1 through figure a.3 . the outputs can drive leds tied to either v dd or gnd. see section 2.2.14, led drivers, page 2-37 for more details on led operation. table a.4 crystal speci?cations parameter spec type parallel resonant frequency 25 mhz 0.01% equivalent series resistance 40 w max load capacitance 18 pf typical case capacitance 7 pf maximum power dissipation 1 mw maximum
draft 6/5/00 a-22 application information copyright ? 2000 by lsi logic corporation. all rights reserved. a.14 repeater applications this section describes how to set up the L80223 to act as a repeater. a.14.1 mii-based repeaters using the standard mii as the interface to the repeater core, the L80223 can be used as the physical interface for mii-based repeaters. for most repeaters, it is necessary to disable the internal crs loopback. to do this, set the txeb_crs bit in the mi serial port con?guration 1 register. for some particular types of repeaters, it may be desirable to either enable or disable autonegotiation, force half-duplex operation, and enable either 100 mbits/s or 10 mbits/s operation. to con?gure any of these modes, set the appropriate bits in the mi serial port control register or appropriately assert or deassert the speed, duplx, and aneg pins on the device. the L80223 has a rptr pin that, when asserted, automatically con?gures the device for one common type of repeater application. when the rptr pin is asserted: tx_en to crs loopback is disabled autonegotiation is disabled half-duplex operation is selected 100 mbits/s operation is selected the mii requires 16 signals between the L80223 and a repeater core. the mii signal count to a repeater core is 16 multiplied by the number of ports, which can be quite large. the signal count between the L80223 and the repeater core can be reduced by 8 per device if the receive output pins are shared and the rx_en pin is used to enable only that port where crs is asserted. refer to section a.9, mii controller interface, page a-15 for more details about using the rx_en pin. a.14.2 non-mii based repeaters the fbi interface available on the L80223 can be used to connect to non-mii based repeaters that employ the industry popular ?ve bit wide interface.
draft 6/5/00 repeater applications a-23 copyright ? 2000 by lsi logic corporation. all rights reserved. because the fbi is a 5-bit interface, it requires that the 4b5b encoder/decoder be bypassed. the fbi is automatically selected on the L80223 when the 4b5b encoder/decoder is bypassed. to bypass the 4b5b encoder/decoder, set the byp_enc bit in the mi serial port con?guration 1 register. some applications may also require the scrambler/descrambler to be bypassed. to bypass the scrambler/descrambler, set the byp_scr bit in the mi serial port con?guration 1 register. for most repeaters, it is necessary to disable the internal crs loopback. to do this, set the tx_en to crs loopback disable bit (txen_crs) in the mi serial port con?guration 1 register. for some particular types of repeaters, it may be desirable to either enable or disable autonegotiation, force half duplex operation, and enable either 100 mbits/s or 10 mbits/s operation. to con?gure any of these modes, set the appropriate bits in the mi serial port control register. the fbi requires 16 signals between the L80223 and a repeater core. the fbi signal count to a repeater core is be 16 multiplied by the number of ports, which can be quite large. the signal count between the L80223 and repeater core can be reduced by 8 per device if the receive output pins are shared and rx_en is used to enable only that port where crs is asserted. refer to section a.9, mii controller interface, page a-15 for more details about using the rx_en pin. a.14.3 clocks normally, transmit data over the mii is clocked into the L80223 on the edge of the transmit output clock (tx_clk). it may be desirable or necessary in some repeater applications to clock in the transmit data from a master clock generated at the repeater core. this requires that transmit data (txd[3:0]) be clocked into the device on edges of the oscin input clock. notice from the timing diagrams that oscin generates tx_clk, and txd[3:0] data is clocked into the L80223 on tx_clk edges. this means that txd data is also clocked in on oscin edges as well. thus, an external clock driving the oscin input can also be used as the clock for txd[3:0].
draft 6/5/00 a-24 application information copyright ? 2000 by lsi logic corporation. all rights reserved. a.15 power supply decoupling there are six v dd pins on the L80223 and six gnd pins. all the v dd pins should be connected together as closely as possible to the device with a large v dd plane. if the v dd pins vary in potential by even a small amount, noise and latchup can result. the v dd pins should be kept to within 50 mv of each other. all the gnd pins should also be connected together as closely as possible to the device with a large ground plane. if the gnd pins vary in potential by even a small amount, noise and latchup can result. the v dd pins should be kept to within 50 mv of each other. a 0.01C0.1 fdecoupling capacitor should be connected between each v dd /gnd set as closely as possible to the device pins, preferably within 0.5 inches. the value should be chosen based on whether the noise from v dd -gnd is high- or low-frequency. a conservative approach would be to use two decoupling capacitors on each v dd /gnd set, one 0.1 ffor low-frequency and one 0.001 ffor high-frequency noise on the power supply. the v dd connection to the transmit transformer center tap shown in figure a.1 through figure a.3 has to be well decoupled to minimize common mode noise injection from the supply into the twisted-pair cable. it is recommended that a 0.01 fdecoupling capacitor be placed between the center tap v dd and the gnd plane. this decoupling capacitor should be physically placed as close as possible to the transformer center tap, preferably within 0.5" the pcb layout and power supply decoupling discussed above should provide suf?cient decoupling to achieve the following when measured at the device: the resultant ac noise voltage measured across each v dd /gnd set should be less than 100 mv p-p all v dd pins should be within 50 mv p-p of each other all gnd pins should be within 50 mv p-p of each other.
copyright ? 2000 by lsi logic corporation. all rights reserved. draft 6/5/00 customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. impor tant: please include your name, phone number, fax number, and company address so that we may contact you directly for clari?cation or additional information. thank you for your help in improving the quality of our documents.
draft 6/5/00 customer feedback rev. letter copyright ? 2000 by lsi logic corporation. all rights reserved. readers comments fax your comments to: lsi logic corporation technical publications m/s e-198 fax: 408.433.4333 please tell us how you rate this document: L80223 10base-t/100base- tx/fx ethernet phy technical manual. place a check mark in the appropriate blank for each category. what could we do to improve this document? if you found errors in this document, please specify the error and page number. if appropriate, please fax a marked-up copy of the page(s). please complete the information below so that we may contact you directly for clari?cation or additional information. excellent good average fair poor completeness of information ____ ____ ____ ____ ____ clarity of information ____ ____ ____ ____ ____ ease of ?nding information ____ ____ ____ ____ ____ technical content ____ ____ ____ ____ ____ usefulness of examples and illustrations ____ ____ ____ ____ ____ overall manual ____ ____ ____ ____ ____ name date telephone title company name street city, state, zip department mail stop fax
u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 spring?eld b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
sales of?ces and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales of?ce m/s c-500 milpitas, ca 95035 tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 dan?eld court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook of?ce park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 tel: 81.6.947.5281 fax: 81.6.947.5287
sales of?ces and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building rijder bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative of?ce room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

▲Up To Search▲

Price & Availability of L80223

	To Download L80223 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .